From a19f4b9eca3c38fc23020a4d841783354d6b6bc0 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Mon, 21 Apr 2025 19:18:40 +0800 Subject: [RV64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and cosim scenario (#2555) --- src/dynarec/rv64/dynarec_rv64_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/dynarec/rv64/dynarec_rv64_helper.c b/src/dynarec/rv64/dynarec_rv64_helper.c index 1b0d1553..944bda40 100644 --- a/src/dynarec/rv64/dynarec_rv64_helper.c +++ b/src/dynarec/rv64/dynarec_rv64_helper.c @@ -1243,7 +1243,7 @@ static void x87_reflectcache(dynarec_rv64_t* dyn, int ninst, int s1, int s2, int SLLI(s1, s3, 3); ADD(s1, xEmu, s1); } - if (extcache_get_st_f(dyn, ninst, dyn->e.x87cache[i]) >= 0) { + if (extcache_get_current_st_f(dyn, dyn->e.x87cache[i]) >= 0) { FCVTDS(SCRATCH0, dyn->e.x87reg[i]); FSD(SCRATCH0, s1, offsetof(x64emu_t, x87)); } else -- cgit 1.4.1