From a2e01c36bae6d886d2f7115427c818be3fbfbfdb Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Wed, 7 Feb 2024 18:01:22 +0100 Subject: [ARM64_DYNAREC] 32bits Shift with 0 amount still wipe upper part of register on 64bits --- src/dynarec/arm64/dynarec_arm64_00.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c index 62604eec..5d36f7df 100644 --- a/src/dynarec/arm64/dynarec_arm64_00.c +++ b/src/dynarec/arm64/dynarec_arm64_00.c @@ -1954,7 +1954,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_rol32c(dyn, ninst, rex, ed, u8, x3, x4); WBACK; } else { - FAKEED; + if(MODREG && ! rex.w && !rex.is32bits) { + GETED(1); + MOVw_REG(ed, ed); + } else { + FAKEED; + } F8; } break; @@ -1968,7 +1973,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_ror32c(dyn, ninst, rex, ed, u8, x3, x4); WBACK; } else { - FAKEED; + if(MODREG && ! rex.w && !rex.is32bits) { + GETED(1); + MOVw_REG(ed, ed); + } else { + FAKEED; + } F8; } break; @@ -2015,7 +2025,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4); WBACK; } else { - FAKEED; + if(MODREG && ! rex.w && !rex.is32bits) { + GETED(1); + MOVw_REG(ed, ed); + } else { + FAKEED; + } F8; } break; @@ -2029,7 +2044,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_shr32c(dyn, ninst, rex, ed, u8, x3, x4); WBACK; } else { - FAKEED; + if(MODREG && ! rex.w && !rex.is32bits) { + GETED(1); + MOVw_REG(ed, ed); + } else { + FAKEED; + } F8; } break; @@ -2043,7 +2063,12 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_sar32c(dyn, ninst, rex, ed, u8, x3, x4); WBACK; } else { - FAKEED; + if(MODREG && ! rex.w && !rex.is32bits) { + GETED(1); + MOVw_REG(ed, ed); + } else { + FAKEED; + } F8; } break; -- cgit 1.4.1