From a6f132f6dab7965d9e19db78ed20b3e0ca045521 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Fri, 2 Jul 2021 15:41:10 +0200 Subject: Added 64 0F AF opcode ([DYNAREC] Too) --- src/dynarec/dynarec_arm64_64.c | 33 +++++++++++++++++++++++++++++++++ src/emu/x64run64.c | 10 ++++++++++ 2 files changed, 43 insertions(+) (limited to 'src') diff --git a/src/dynarec/dynarec_arm64_64.c b/src/dynarec/dynarec_arm64_64.c index 2fab3ee3..e735784d 100644 --- a/src/dynarec/dynarec_arm64_64.c +++ b/src/dynarec/dynarec_arm64_64.c @@ -151,6 +151,39 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0xAF: + INST_NAME("IMUL Gd, Ed"); + SETFLAGS(X_ALL, SF_PENDING); + nextop = F8; + grab_segdata(dyn, addr, ninst, x4, seg); + GETGD; + GETEDO(x4, 0); + if(rex.w) { + // 64bits imul + UFLAG_IF { + SMULH(x3, gd, ed); + MULx(gd, gd, ed); + UFLAG_OP1(x3); + UFLAG_RES(gd); + UFLAG_DF(x3, d_imul64); + } else { + MULxw(gd, gd, ed); + } + } else { + // 32bits imul + UFLAG_IF { + SMULL(gd, gd, ed); + UFLAG_RES(gd); + LSRx(x3, gd, 32); + UFLAG_OP1(x3); + UFLAG_DF(x3, d_imul32); + MOVw_REG(gd, gd); + } else { + MULxw(gd, gd, ed); + } + } + break; + default: DEFAULT; } diff --git a/src/emu/x64run64.c b/src/emu/x64run64.c index c7f2fbec..63b95199 100644 --- a/src/emu/x64run64.c +++ b/src/emu/x64run64.c @@ -181,6 +181,16 @@ int Run64(x64emu_t *emu, rex_t rex, int seg) } break; + case 0xAF: /* IMUL Gd,Ed */ + nextop = F8; + GETED_OFFS(0, tlsdata); + GETGD; + if(rex.w) + GD->q[0] = imul64(emu, GD->q[0], ED->q[0]); + else + GD->q[0] = imul32(emu, GD->dword[0], ED->dword[0]); + break; + default: return 1; } -- cgit 1.4.1