From aa5d320707824b9dbe3da44956fb69021401d227 Mon Sep 17 00:00:00 2001 From: xctan Date: Thu, 13 Apr 2023 16:33:45 +0800 Subject: [RV64_DYNAREC] Added more opcodes for SV (#693) * [RV64_DYNAREC] Added 0F 5A CVTPS2PD opcode * [RV64_DYNAREC] Added F8 CLC opcode * [RV64_DYNAREC] Added 0F AE /{0,1} FXSAVE and FXRSTOR opcodes * [RV64_DYNAREC] Added 9D POPF opcode * [RV64_DYNAREC] Added 11 ADC opcode * [RV64_DYNAREC] Revert "Added 0F AE /{0,1} FXSAVE and FXRSTOR opcodes" * [RV64_DYNAREC] Fixed flags handling and CVTPS2PD --- src/dynarec/arm64/dynarec_arm64_00.c | 1 + src/dynarec/rv64/dynarec_rv64_00.c | 29 +++++++++++++++++++++++++++++ src/dynarec/rv64/dynarec_rv64_0f.c | 17 ++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_00.c b/src/dynarec/arm64/dynarec_arm64_00.c index a4e7d6b0..7696a6ec 100755 --- a/src/dynarec/arm64/dynarec_arm64_00.c +++ b/src/dynarec/arm64/dynarec_arm64_00.c @@ -1148,6 +1148,7 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin case 0x9C: INST_NAME("PUSHF"); READFLAGS(X_ALL); + PUSH1(xFlags); break; case 0x9D: diff --git a/src/dynarec/rv64/dynarec_rv64_00.c b/src/dynarec/rv64/dynarec_rv64_00.c index 3adc4646..2bb6d9ea 100644 --- a/src/dynarec/rv64/dynarec_rv64_00.c +++ b/src/dynarec/rv64/dynarec_rv64_00.c @@ -170,6 +170,18 @@ uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni DEFAULT; } break; + + case 0x11: + INST_NAME("ADC Ed, Gd"); + READFLAGS(X_CF); + SETFLAGS(X_ALL, SF_SET_PENDING); + nextop = F8; + GETGD; + GETED(0); + emit_adc32(dyn, ninst, rex, ed, gd, x3, x4, x5); + WBACK; + break; + case 0x18: INST_NAME("SBB Eb, Gb"); READFLAGS(X_CF); @@ -956,8 +968,19 @@ uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni case 0x9C: INST_NAME("PUSHF"); READFLAGS(X_ALL); + FLAGS_ADJUST_TO11(xFlags, x2); PUSH1(xFlags); break; + case 0x9D: + INST_NAME("POPF"); + SETFLAGS(X_ALL, SF_SET); + POP1(xFlags); + FLAGS_ADJUST_FROM11(xFlags, x2); + MOV32w(x1, 0x3F7FD7); + AND(xFlags, xFlags, x1); + ORI(xFlags, xFlags, 0x2); + SET_DFNONE(); + break; case 0xA4: if(rep) { INST_NAME("REP MOVSB"); @@ -1888,6 +1911,12 @@ uintptr_t dynarec64_00(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni }; break; + case 0xF8: + INST_NAME("CLC"); + SETFLAGS(X_CF, SF_SUBSET); + SET_DFNONE(); + ANDI(xFlags, xFlags, ~(1 << F_CF)); + break; case 0xF9: INST_NAME("STC"); SETFLAGS(X_CF, SF_SUBSET); diff --git a/src/dynarec/rv64/dynarec_rv64_0f.c b/src/dynarec/rv64/dynarec_rv64_0f.c index 55c15191..2e8aae41 100644 --- a/src/dynarec/rv64/dynarec_rv64_0f.c +++ b/src/dynarec/rv64/dynarec_rv64_0f.c @@ -39,7 +39,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni int v0, v1; int q0, q1; int d0, d1; - int s0; + int s0, s1; uint64_t tmp64u; int64_t j64; int64_t fixedaddress; @@ -344,6 +344,21 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni } break; + case 0x5A: + INST_NAME("CVTPS2PD Gx, Ex"); + nextop = F8; + GETGX(x1); + GETEX(x2, 0); + s0 = fpu_get_scratch(dyn); + s1 = fpu_get_scratch(dyn); + FLW(s0, wback, fixedaddress); + FLW(s1, wback, fixedaddress+4); + FCVTDS(s0, s0); + FCVTDS(s1, s1); + FSD(s0, gback, 0); + FSD(s1, gback, 8); + break; + case 0x77: INST_NAME("EMMS"); // empty MMX, FPU now usable -- cgit 1.4.1