From adea4ceef2b17111a60298f8ea57225f923e80fb Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Thu, 18 Mar 2021 17:35:39 +0100
Subject: [DYNAREC] Fixed PF flags computation

---
 src/dynarec/dynarec_arm64_emit_math.c | 2 +-
 src/dynarec/dynarec_arm64_helper.c    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/dynarec/dynarec_arm64_emit_math.c b/src/dynarec/dynarec_arm64_emit_math.c
index 4e172e56..fcd2a73c 100755
--- a/src/dynarec/dynarec_arm64_emit_math.c
+++ b/src/dynarec/dynarec_arm64_emit_math.c
@@ -904,7 +904,7 @@ void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
         ANDxw_REG(s3, s3, s1);   // s3 = (~op1 | op2) & res
         ORRxw_REG(s3, s3, s4);   // s4 = (~op1 & op2) | ((~op1 | op2) & ~ res)
         LSRxw(s4, s3, 3);
-        BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
     IFX(X_ZF|X_OF) {
         MOV32w(s3, (1<<F_ZF)|(1<<F_OF));
diff --git a/src/dynarec/dynarec_arm64_helper.c b/src/dynarec/dynarec_arm64_helper.c
index 2f257929..24aca546 100755
--- a/src/dynarec/dynarec_arm64_helper.c
+++ b/src/dynarec/dynarec_arm64_helper.c
@@ -977,7 +977,7 @@ void fpu_reset(dynarec_arm_t* dyn, int ninst)
 void emit_pf(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
     // PF: (((emu->x64emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
-    ANDw_mask(s3, s1, 0b011011, 000010); // lsr 5 masking pre-applied
+    ANDw_mask(s3, s1, 0b011011, 0b000010); // mask=0xE0
     LSRw(s3, s3, 5);
     MOV64x(s4, (uintptr_t)GetParityTab());
     LDRw_REG_LSL2(s4, s4, s3);
-- 
cgit 1.4.1