From b1ae5dc2b6335057305eb62b861c2eff166b8e0a Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sun, 23 Jun 2024 12:04:42 +0200 Subject: [ARM64_DYNAREC] Small optim on 0F BC/BD opcodes --- src/dynarec/arm64/dynarec_arm64_0f.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index a3e86df2..3547b670 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -2148,8 +2148,10 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin RBITxw(x1, ed); // reverse CLZxw(gd, x1); // x2 gets leading 0 == BSF MARK; - CSETw(x1, cEQ); //ZF not set - BFIw(xFlags, x1, F_ZF, 1); + IFX(X_ZF) { + CSETw(x1, cEQ); //ZF not set + BFIw(xFlags, x1, F_ZF, 1); + } break; case 0xBD: INST_NAME("BSR Gd, Ed"); @@ -2164,8 +2166,10 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin SUBxw_U12(gd, gd, rex.w?63:31); NEGxw_REG(gd, gd); // complement MARK; - CSETw(x1, cEQ); //ZF not set - BFIw(xFlags, x1, F_ZF, 1); + IFX(X_ZF) { + CSETw(x1, cEQ); //ZF not set + BFIw(xFlags, x1, F_ZF, 1); + } break; case 0xBE: INST_NAME("MOVSX Gd, Eb"); -- cgit 1.4.1