From b247fd04df986b75bed76c5768479472d6987f65 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Mon, 22 Mar 2021 16:00:19 +0100
Subject: [DYNAREC] Added 0F 56 opcode

---
 src/dynarec/arm64_emitter.h    | 18 ++++++++++++++++++
 src/dynarec/arm64_printer.c    | 17 ++++++++++++++++-
 src/dynarec/dynarec_arm64_0f.c | 23 +++++++++++++++--------
 3 files changed, 49 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/dynarec/arm64_emitter.h b/src/dynarec/arm64_emitter.h
index d61d299c..7313854a 100755
--- a/src/dynarec/arm64_emitter.h
+++ b/src/dynarec/arm64_emitter.h
@@ -593,6 +593,9 @@
 #define VEORQ(Vd, Vn, Vm)                   EMIT(VLOGIC_gen(1, 0b00, Vm, Vn, Vd))
 #define VEOR(Vd, Vn, Vm)                    EMIT(VLOGIC_gen(0, 0b00, Vm, Vn, Vd))
 
+#define VLOGIC_immediate(Q, op, abc, cmade, defgh, Rd)  ((Q)<<30 | (op)<<29 | 0b0111100000<<19 | (abc)<<16 | (cmode)<<12 | 1<<10 | (defgh)<<5 | (Rd))
+//#define V
+
 // FMOV
 #define FMOV_general(sf, type, mode, opcode, Rn, Rd)    ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (mode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
 // 32-bit to single-precision
@@ -638,6 +641,21 @@
 #define VMOVQ(Vd, Vn)               EMIT(ORR_vector(1, Vn, Vn, Vd))
 #define VMOV(Dd, Dn)                EMIT(ORR_vector(0, Dn, Dn, Dd))
 
+// VAND
+#define AND_vector(Q, Rm, Rn, Rd)   ((Q)<<30 | 0b01110<<24 | 0b00<<22 | 1<<21 | (Rm)<<16 | 0b00011<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VANDQ(Vd, Vn, Vm)           EMIT(AND_vector(1, Vm, Vn, Vd))
+#define VAND(Dd, Dn, Dm)            EMIT(AND_vector(0, Dm, Dn, Dd))
+
+// VBIC
+#define BIC_vector(Q, Rm, Rn, Rd)   ((Q)<<30 | 0b01110<<24 | 0b01<<22 | 1<<21 | (Rm)<<16 | 0b00011<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VBICQ(Vd, Vn, Vm)           EMIT(BIC_vector(1, Vm, Vn, Vd))
+#define VBIC(Dd, Dn, Dm)            EMIT(BIC_vector(0, Dm, Dn, Dd))
+
+// VORN
+#define ORN_vector(Q, Rm, Rn, Rd)   ((Q)<<30 | 0b01110<<24 | 0b11<<22 | 1<<21 | (Rm)<<16 | 0b00011<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VORNQ(Vd, Vn, Vm)           EMIT(ORN_vector(1, Vm, Vn, Vd))
+#define VORN(Dd, Dn, Dm)            EMIT(ORN_vector(0, Dm, Dn, Dd))
+
 // ADD / SUB
 #define FADDSUB_vector(Q, U, op, sz, Rm, Rn, Rd)   ((Q)<<30 | (U)<<29 | 0b01110<<24 | (op)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11010<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFADDQS(Vd, Vn, Vm)         EMIT(FADDSUB_vector(1, 0, 0, 0, Vm, Vn, Vd))
diff --git a/src/dynarec/arm64_printer.c b/src/dynarec/arm64_printer.c
index 79f2d6ec..e217726e 100755
--- a/src/dynarec/arm64_printer.c
+++ b/src/dynarec/arm64_printer.c
@@ -745,7 +745,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
 
     //  ----------- NEON / FPU
 
-    // VORR
+    // VORR/VAND/VBIC/VORN
     if(isMask(opcode, "0Q001110101mmmmm000111nnnnnddddd", &a)) {
         char q = a.Q?'Q':'D';
         if(Rn==Rm)
@@ -754,6 +754,21 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "VORR %c%d, %c%d, %c%d", q, Rd, q, Rn, q, Rm);
         return buff;
     }
+    if(isMask(opcode, "0Q001110111mmmmm000111nnnnnddddd", &a)) {
+        char q = a.Q?'Q':'D';
+        snprintf(buff, sizeof(buff), "VORN %c%d, %c%d, %c%d", q, Rd, q, Rn, q, Rm);
+        return buff;
+    }
+    if(isMask(opcode, "0Q001110001mmmmm000111nnnnnddddd", &a)) {
+        char q = a.Q?'Q':'D';
+        snprintf(buff, sizeof(buff), "VAND %c%d, %c%d, %c%d", q, Rd, q, Rn, q, Rm);
+        return buff;
+    }
+    if(isMask(opcode, "0Q001110011mmmmm000111nnnnnddddd", &a)) {
+        char q = a.Q?'Q':'D';
+        snprintf(buff, sizeof(buff), "VBIC %c%d, %c%d, %c%d", q, Rd, q, Rn, q, Rm);
+        return buff;
+    }
     // UMOV
     if(isMask(opcode, "0Q001110000rrrrr001111nnnnnddddd", &a)) {
         char q = a.Q?'Q':'D';
diff --git a/src/dynarec/dynarec_arm64_0f.c b/src/dynarec/dynarec_arm64_0f.c
index b73b3286..eb7f034b 100755
--- a/src/dynarec/dynarec_arm64_0f.c
+++ b/src/dynarec/dynarec_arm64_0f.c
@@ -199,6 +199,21 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         GOCOND(0x40, "CMOV", "Gd, Ed");
         #undef GO
         
+        case 0x56:
+            INST_NAME("ORPS Gx, Ex");
+            nextop = F8;
+            GETEX(q0, 0);
+            GETGX(v0);
+            VORRQ(v0, v0, q0);
+            break;
+        case 0x57:
+            INST_NAME("XORPS Gx, Ex");
+            nextop = F8;
+            GETEX(q0, 0);
+            GETGX(v0);
+            VEORQ(v0, v0, q0);
+            break;
+
         #define GO(GETFLAGS, NO, YES, F)   \
             READFLAGS(F);   \
             i32_ = F32S;    \
@@ -244,14 +259,6 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         GOCOND(0x90, "SET", "Eb");
         #undef GO
             
-        case 0x57:
-            INST_NAME("XORPS Gx, Ex");
-            nextop = F8;
-            GETEX(q0, 0);
-            GETGX(v0);
-            VEORQ(v0, v0, q0);
-            break;
-
         case 0xA2:
             INST_NAME("CPUID");
             MOVx_REG(x1, xRAX);
-- 
cgit 1.4.1