From bd4454d8ad925cb17ccf3beaa6c872440fede753 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 10 Aug 2024 09:34:09 +0200 Subject: [ARM64_DYNAREC] Fixed pending flags for large 8 & 16 bit const shifts --- src/dynarec/arm64/dynarec_arm64_emit_shift.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_emit_shift.c b/src/dynarec/arm64/dynarec_arm64_emit_shift.c index 84166055..5516a8ce 100644 --- a/src/dynarec/arm64/dynarec_arm64_emit_shift.c +++ b/src/dynarec/arm64/dynarec_arm64_emit_shift.c @@ -366,6 +366,9 @@ void emit_shl8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s BFXILw(xFlags, s3, 7, 1); // insert F_CF from s3[7:1] } MOVw_REG(s1, xZR); + IFX(X_PEND) { + STRB_U12(s1, xEmu, offsetof(x64emu_t, res)); + } IFX(X_OF) { BFCw(xFlags, F_OF, 1); } @@ -630,6 +633,9 @@ void emit_shl16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int BFXILw(xFlags, s3, 15, 1); // insert F_CF from s3[15:1] } MOVw_REG(s1, xZR); + IFX(X_PEND) { + STRH_U12(s1, xEmu, offsetof(x64emu_t, res)); + } IFX(X_OF) { BFCw(xFlags, F_OF, 1); } -- cgit 1.4.1