From c02b350b3da701464d54dbfe463b378eb0f2d325 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Sun, 26 Mar 2023 16:13:24 +0200
Subject: [ARM64_DYNAREC] Fixed flag handling of PTEST opcode

---
 src/dynarec/arm64/dynarec_arm64_660f.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c
index 59e299d3..f703ac09 100755
--- a/src/dynarec/arm64/dynarec_arm64_660f.c
+++ b/src/dynarec/arm64/dynarec_arm64_660f.c
@@ -332,7 +332,7 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                 case 0x17:
                     INST_NAME("PTEST Gx, Ex");
                     nextop = F8;
-                    SETFLAGS(X_ZF|X_CF, SF_SUBSET);
+                    SETFLAGS(X_ALL, SF_SET);
                     GETGX(q0, 0);
                     GETEX(q1, 0, 0);
                     v1 = fpu_get_scratch(dyn);
@@ -352,6 +352,11 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                         UBFXx(x1, x1, 33, 1);
                         BFIw(xFlags, x1, F_CF, 1);
                     }
+                    IFX(X_PF|X_AF|X_OF|X_SF) {
+                        MOV32w(x1, (1<<F_PF)|(1<<F_AF)|(1<<F_OF)|(1<<F_SF));
+                        BICw_REG(xFlags, xFlags, x1);
+                    }
+                    SET_DFNONE(x1);
                     break;
 
                 case 0x1C:
-- 
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