From d39c55454182d689ee923e19e1c52a187daaa8ae Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 22 Jun 2024 13:26:58 +0200 Subject: [ARM64_DYNAREC] Small improvement to 0F 5D/5F opcodes --- src/dynarec/arm64/dynarec_arm64_0f.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index 3fe4d540..a3e86df2 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -1128,14 +1128,12 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin GETEX(v1, 0, 0); // FMIN/FMAX wll not copy the value if v0[x] is NaN // but x86 will copy if either v0[x] or v1[x] is NaN, so lets force a copy if source is NaN - if(!box64_dynarec_fastnan && v0!=v1) { + VFMINQS(v0, v0, v1); + if(!box64_dynarec_fastnan && (v0!=v1)) { q0 = fpu_get_scratch(dyn, ninst); VFCMEQQS(q0, v0, v0); // 0 is NaN, 1 is not NaN, so MASK for NaN - VANDQ(v0, v0, q0); - VBICQ(q0, v1, q0); - VORRQ(v0, v0, q0); + VBIFQ(v0, v1, q0); // copy dest where source is NaN } - VFMINQS(v0, v0, v1); break; case 0x5E: INST_NAME("DIVPS Gx, Ex"); @@ -1151,14 +1149,12 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin GETEX(v1, 0, 0); // FMIN/FMAX wll not copy the value if v0[x] is NaN // but x86 will copy if either v0[x] or v1[x] is NaN, so lets force a copy if source is NaN - if(!box64_dynarec_fastnan && v0!=v1) { + VFMAXQS(v0, v0, v1); + if(!box64_dynarec_fastnan && (v0!=v1)) { q0 = fpu_get_scratch(dyn, ninst); VFCMEQQS(q0, v0, v0); // 0 is NaN, 1 is not NaN, so MASK for NaN - VANDQ(v0, v0, q0); - VBICQ(q0, v1, q0); - VORRQ(v0, v0, q0); + VBIFQ(v0, v1, q0); // copy dest where source is NaN } - VFMAXQS(v0, v0, v1); break; case 0x60: INST_NAME("PUNPCKLBW Gm,Em"); -- cgit 1.4.1