From d62e9652fcbcaad8fd5c83956d476eb11499a85f Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Fri, 14 Jul 2023 11:18:30 +0200 Subject: [ARM64_DYNAREC] Added 66 9C/9D opcodes (mostly for 32bits) --- src/dynarec/arm64/arm64_emitter.h | 3 +++ src/dynarec/arm64/dynarec_arm64_66.c | 23 +++++++++++++++++++++++ 2 files changed, 26 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64/arm64_emitter.h b/src/dynarec/arm64/arm64_emitter.h index af35b140..3b9b6049 100755 --- a/src/dynarec/arm64/arm64_emitter.h +++ b/src/dynarec/arm64/arm64_emitter.h @@ -363,6 +363,9 @@ #define POP2_32(reg1, reg2) LDPw_S7_postindex(reg1, reg2, xRSP, 8) #define PUSH2_32(reg1, reg2) STPw_S7_preindex(reg2, reg1, xRSP, -8) +#define POP1_16(reg) LDRH_S9_postindex(reg, xRSP, 2) +#define PUSH1_16(reg) STRH_S9_preindex(reg, xRSP, -2) + #define POP1z(reg) if(rex.is32bits) {POP1_32(reg);} else {POP1(reg);} #define PUSH1z(reg) if(rex.is32bits) {PUSH1_32(reg);} else {PUSH1(reg);} #define POP2z(reg1, reg2) if(rex.is32bits) {POP2_32(reg1, reg2);} else {POP2(reg1, reg2);} diff --git a/src/dynarec/arm64/dynarec_arm64_66.c b/src/dynarec/arm64/dynarec_arm64_66.c index 17aef347..ff269cf2 100755 --- a/src/dynarec/arm64/dynarec_arm64_66.c +++ b/src/dynarec/arm64/dynarec_arm64_66.c @@ -592,6 +592,29 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin BFIw(xRAX, x1, 0, 16); break; + case 0x9C: + INST_NAME("PUSHF"); + READFLAGS(X_ALL); + PUSH1_16(xFlags); + break; + case 0x9D: + INST_NAME("POPF"); + SETFLAGS(X_ALL, SF_SET); + POP1_16(x1); // probably not usefull... + BFIw(xFlags, x1, 0, 16); + MOV32w(x1, 0x3F7FD7); + ANDw_REG(xFlags, xFlags, x1); + ORRw_mask(xFlags, xFlags, 0b011111, 0); //mask=0x00000002 + SET_DFNONE(x1); + if(box64_wine) { // should this be done all the time? + TBZ_NEXT(xFlags, F_TF); + MOV64x(x1, addr); + STORE_XEMU_CALL(x1); + CALL(native_singlestep, -1); + BFCw(xFlags, F_TF, 1); + } + break; + case 0xA1: INST_NAME("MOV EAX,Od"); if(rex.is32bits) -- cgit 1.4.1