From d67615c976c6e97bba0035693e22ce88371cf871 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 24 Jun 2023 13:03:00 +0200 Subject: [32BITS][ARM64_DYNAREC] Added 64 A1/A3 opcode --- src/dynarec/arm64/dynarec_arm64_64.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_64.c b/src/dynarec/arm64/dynarec_arm64_64.c index 81de278b..3b2dc9ed 100644 --- a/src/dynarec/arm64/dynarec_arm64_64.c +++ b/src/dynarec/arm64/dynarec_arm64_64.c @@ -35,6 +35,7 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin uint8_t gd, ed, eb1, eb2, gb1, gb2; uint8_t wback, wb1, wb2, wb; int64_t i64, j64; + uint64_t u64; int v0, v1; int q0; int d0; @@ -593,6 +594,29 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin } break; + case 0xA1: + INST_NAME("MOV EAX,FS:Od"); + grab_segdata(dyn, addr, ninst, x4, seg); + if(rex.is32bits) + u64 = F32; + else + u64 = F64; + MOV64z(x1, u64); + LDRxw_REG(xRAX, x1, x4); + break; + + case 0xA3: + INST_NAME("MOV FS:Od,EAX"); + grab_segdata(dyn, addr, ninst, x4, seg); + if(rex.is32bits) + u64 = F32; + else + u64 = F64; + MOV64z(x1, u64); + STRxw_REG(xRAX, x1, x4); + SMWRITE2(); + break; + case 0xC6: INST_NAME("MOV Seg:Eb, Ib"); grab_segdata(dyn, addr, ninst, x4, seg); -- cgit 1.4.1