From dd9e8ae8ffe211ffd1e69c637ad9b425a6e8e907 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Thu, 18 Mar 2021 12:18:30 +0100 Subject: [DYNAREC] Added 09/0B/0D OR and 21/23/25 AND opcodes --- src/dynarec/dynarec_arm64_00.c | 52 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'src') diff --git a/src/dynarec/dynarec_arm64_00.c b/src/dynarec/dynarec_arm64_00.c index 27964f60..bfc53bfc 100755 --- a/src/dynarec/dynarec_arm64_00.c +++ b/src/dynarec/dynarec_arm64_00.c @@ -83,6 +83,58 @@ uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin emit_add32c(dyn, ninst, rex, xRAX, i32, x3, x4, x5); break; + case 0x09: + INST_NAME("OR Ed, Gd"); + SETFLAGS(X_ALL, SF_SET); + nextop = F8; + GETGD; + GETED(0); + emit_or32(dyn, ninst, rex, ed, gd, x3, x4); + WBACK; + break; + + case 0x0B: + INST_NAME("OR Gd, Ed"); + SETFLAGS(X_ALL, SF_SET); + nextop = F8; + GETGD; + GETED(0); + emit_or32(dyn, ninst, rex, gd, ed, x3, x4); + break; + + case 0x0D: + INST_NAME("OR EAX, Id"); + SETFLAGS(X_ALL, SF_SET); + i32 = F32S; + emit_or32c(dyn, ninst, rex, xRAX, i32, x3, x4); + break; + + case 0x21: + INST_NAME("AND Ed, Gd"); + SETFLAGS(X_ALL, SF_SET); + nextop = F8; + GETGD; + GETED(0); + emit_and32(dyn, ninst, rex, ed, gd, x3, x4); + WBACK; + break; + + case 0x23: + INST_NAME("AND Gd, Ed"); + SETFLAGS(X_ALL, SF_SET); + nextop = F8; + GETGD; + GETED(0); + emit_and32(dyn, ninst, rex, gd, ed, x3, x4); + break; + + case 0x25: + INST_NAME("AND EAX, Id"); + SETFLAGS(X_ALL, SF_SET); + i32 = F32S; + emit_and32c(dyn, ninst, rex, xRAX, i32, x3, x4); + break; + case 0x29: INST_NAME("SUB Ed, Gd"); SETFLAGS(X_ALL, SF_SET); -- cgit 1.4.1