From e1b6976528322ad8fe2217afcefa5bdcdfa95139 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Fri, 8 Aug 2025 05:18:32 +0800 Subject: [LA64_DYNAREC] Fixed AVX VCMPSS/VCMPSD opcodes (#2914) --- src/dynarec/la64/dynarec_la64_avx_f2_0f.c | 3 ++- src/dynarec/la64/dynarec_la64_avx_f3_0f.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/dynarec/la64/dynarec_la64_avx_f2_0f.c b/src/dynarec/la64/dynarec_la64_avx_f2_0f.c index 372b4034..0796e67f 100644 --- a/src/dynarec/la64/dynarec_la64_avx_f2_0f.c +++ b/src/dynarec/la64/dynarec_la64_avx_f2_0f.c @@ -398,7 +398,7 @@ uintptr_t dynarec64_AVX_F2_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, nextop = F8; GETVYx(v1, 0); GETEYSD(v2, 0, 1); - GETGYx_empty(v0); + GETGYx(v0, 1); q0 = fpu_get_scratch(dyn); u8 = F8; switch (u8 & 0xf) { @@ -420,6 +420,7 @@ uintptr_t dynarec64_AVX_F2_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, case 0x0f: VSEQ_B(q0, v1, v1); break; // true } XVXOR_V(v0, v0, v0); + XVPERMI_Q(v0, v1, XVPERMI_IMM_4_0(3, 0)); XVINSVE0_D(v0, q0, 0); YMM_UNMARK_UPPER_ZERO(v0); break; diff --git a/src/dynarec/la64/dynarec_la64_avx_f3_0f.c b/src/dynarec/la64/dynarec_la64_avx_f3_0f.c index 7432dc87..460726fd 100644 --- a/src/dynarec/la64/dynarec_la64_avx_f3_0f.c +++ b/src/dynarec/la64/dynarec_la64_avx_f3_0f.c @@ -451,7 +451,7 @@ uintptr_t dynarec64_AVX_F3_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, nextop = F8; GETVYx(v1, 0); GETEYSS(v2, 0, 1); - GETGYx_empty(v0); + GETGYx(v0, 1); q0 = fpu_get_scratch(dyn); u8 = F8; switch (u8 & 0xf) { @@ -473,6 +473,7 @@ uintptr_t dynarec64_AVX_F3_0F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, case 0x0f: VSEQ_B(q0, v1, v1); break; // true } XVXOR_V(v0, v0, v0); + XVPERMI_Q(v0, v1, XVPERMI_IMM_4_0(3, 0)); XVINSVE0_W(v0, q0, 0); YMM_UNMARK_UPPER_ZERO(v0); break; -- cgit 1.4.1