From e8a7bef5a072b21c4e62ae3874aec51b95e9f6b9 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 8 Mar 2025 20:58:04 +0100 Subject: [ARM64_DYNAREC] Fixed a potential issue with AVX.0F 50 opcode --- src/dynarec/arm64/dynarec_arm64_avx_0f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_avx_0f.c b/src/dynarec/arm64/dynarec_arm64_avx_0f.c index 387faf1b..79b9988f 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_avx_0f.c @@ -302,7 +302,7 @@ uintptr_t dynarec64_AVX_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int // EX is an xmm reg q0 = fpu_get_scratch(dyn, ninst); for(int l=0; l<1+vex.l; ++l) { - if(!l) { GETEX(v0, 0, 0); } else { GETEY(v0); } + if(!l) { GETEX_Y(v0, 0, 0); } else { GETEY(v0); } SQXTN_16(q0, v0); // reduces the 4 32bits to 4 16bits VMOVQDto(x1, q0, 0); LSRx(x1, x1, 15); -- cgit 1.4.1