From ed452e81ae59982da75774ad52f6bfafe24096fb Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Tue, 23 Mar 2021 11:03:55 +0100 Subject: [DYNAREC] Improved CMPLESS accuracy --- src/dynarec/dynarec_arm64_f30f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c index 24cb0e67..3ff24d0a 100755 --- a/src/dynarec/dynarec_arm64_f30f.c +++ b/src/dynarec/dynarec_arm64_f30f.c @@ -209,11 +209,11 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n } else { FCMPS(v0, v1); } - MOV32w(x2, 0); switch(u8&7) { case 0: CSETMw(x2, cEQ); break; // Equal case 1: CSETMw(x2, cMI); break; // Less than - case 2: CSETMw(x2, cLE); break; // Less or equal + case 2: //CSETMw(x2, cLE); break; // Less or equal (or unordered on ARM64, not on x86...) + CSETMw(x2, cPL); CSINVw(x2, xZR, x2, cEQ); break; // so use a 2 step here, but 1st test inverted because 2nd step invert again case 3: CSETMw(x2, cVS); break; // NaN case 4: CSETMw(x2, cNE); break; // Not Equal (or unordered on ARM, not on X86...) case 5: CSETMw(x2, cCS); break; // Greater or equal or unordered -- cgit 1.4.1