From efa6ee7275f034bdbd213fbed4ebbf3379855189 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Wed, 9 Jul 2025 11:24:23 +0200 Subject: [ARM64_DYNAREC] Fixed rare sideeffect of 32bits cmpxchg opcode --- src/dynarec/arm64/dynarec_arm64_0f.c | 3 ++- src/dynarec/arm64/dynarec_arm64_f0.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index ccff6c02..c8df4f9f 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -2079,7 +2079,8 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin CMPSxw_REG(xRAX, ed); } MOVxw_REG(x1, ed); // save value - CSELxw(ed, gd, ed, cEQ); + Bcond(cNE, 4+4); + MOVxw_REG(ed, gd); } else { addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 0); LDxw(x1, wback, fixedaddress); diff --git a/src/dynarec/arm64/dynarec_arm64_f0.c b/src/dynarec/arm64/dynarec_arm64_f0.c index 6fcb3df4..7b9632cc 100644 --- a/src/dynarec/arm64/dynarec_arm64_f0.c +++ b/src/dynarec/arm64/dynarec_arm64_f0.c @@ -342,7 +342,8 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin CMPSxw_REG(xRAX, ed); } MOVxw_REG(x1, ed); // save value - CSELxw(ed, gd, ed, cEQ); + Bcond(cNE, 4+4); + MOVxw_REG(ed, gd); MOVxw_REG(xRAX, x1); } else { addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0); -- cgit 1.4.1