From f7acb787432b3cf2b5b8127d80476d80e362dd1e Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Sat, 26 Apr 2025 10:39:44 +0200 Subject: [ARM64_DYNAREC] Small fix for edge cases on (V)PMULHUW opcodes --- src/dynarec/arm64/dynarec_arm64_0f.c | 6 ++---- src/dynarec/arm64/dynarec_arm64_660f.c | 6 ++++-- src/dynarec/arm64/dynarec_arm64_avx_66_0f.c | 6 ++++-- 3 files changed, 10 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_0f.c b/src/dynarec/arm64/dynarec_arm64_0f.c index b4778849..5d983399 100644 --- a/src/dynarec/arm64/dynarec_arm64_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_0f.c @@ -2813,11 +2813,9 @@ uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin GETGM(v0); GETEM(v1, 0); q0 = fpu_get_scratch(dyn, ninst); - q1 = fpu_get_scratch(dyn, ninst); VUMULL_16(q0, v0, v1); - VUMULL2_16(q1, v0, v1); - UQSHRN_16(v0, q0, 16); - UQSHRN2_16(v0, q1, 16); + VSHRQ_32(q0, q0, 16); + XTN_16(v0, q0); break; case 0xE5: INST_NAME("PMULHW Gm,Em"); diff --git a/src/dynarec/arm64/dynarec_arm64_660f.c b/src/dynarec/arm64/dynarec_arm64_660f.c index fddd347a..d36dea7b 100644 --- a/src/dynarec/arm64/dynarec_arm64_660f.c +++ b/src/dynarec/arm64/dynarec_arm64_660f.c @@ -3108,8 +3108,10 @@ uintptr_t dynarec64_660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n q1 = fpu_get_scratch(dyn, ninst); VUMULL_16(q0, v0, v1); VUMULL2_16(q1, v0, v1); - UQSHRN_16(v0, q0, 16); - UQSHRN2_16(v0, q1, 16); + VSHRQ_32(q0, q0, 16); + VSHRQ_32(q1, q1, 16); + XTN_16(v0, q0); + XTN2_16(v0, q1); break; case 0xE5: INST_NAME("PMULHW Gx, Ex"); diff --git a/src/dynarec/arm64/dynarec_arm64_avx_66_0f.c b/src/dynarec/arm64/dynarec_arm64_avx_66_0f.c index 7f33f8d3..aea2f378 100644 --- a/src/dynarec/arm64/dynarec_arm64_avx_66_0f.c +++ b/src/dynarec/arm64/dynarec_arm64_avx_66_0f.c @@ -1626,8 +1626,10 @@ uintptr_t dynarec64_AVX_66_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, if(!l) { GETGX_empty_VXEX(v0, v2, v1, 0); } else { GETGY_empty_VYEY(v0, v2, v1); } VUMULL_16(q0, v2, v1); VUMULL2_16(q1, v2, v1); - UQSHRN_16(v0, q0, 16); - UQSHRN2_16(v0, q1, 16); + VSHRQ_32(q0, q0, 16); + VSHRQ_32(q1, q1, 16); + XTN_16(v0, q0); + XTN2_16(v0, q1); } if(!vex.l) YMM0(gd); break; -- cgit 1.4.1