From f88f59926eb6f61a7c71aeea2462681dc78d6cd9 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Tue, 23 Mar 2021 11:30:48 +0100
Subject: [DYNAREC] Added F3 0F 5D opcode

---
 src/dynarec/dynarec_arm64_f30f.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/dynarec/dynarec_arm64_f30f.c b/src/dynarec/dynarec_arm64_f30f.c
index 3ff24d0a..a0aa0d7f 100755
--- a/src/dynarec/dynarec_arm64_f30f.c
+++ b/src/dynarec/dynarec_arm64_f30f.c
@@ -148,7 +148,16 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             FSUBS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
-
+        case 0x5D:
+            INST_NAME("MINSS Gx, Ex");
+            nextop = F8;
+            GETGX(v0);
+            GETEX(v1, 0);
+            // MINSS: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
+            d0 = fpu_get_scratch(dyn);
+            FMINNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
+            VMOVeS(v0, 0, d0, 0);   // to not erase uper part
+            break;
         case 0x5E:
             INST_NAME("DIVSS Gx, Ex");
             nextop = F8;
-- 
cgit 1.4.1