From f8bdb8bd1647b7932b11292b05155e2844095156 Mon Sep 17 00:00:00 2001 From: ptitSeb Date: Fri, 7 Apr 2023 12:58:39 +0200 Subject: [ARM64_DYNAREC] Fixed 66 0F 5B opcode when FASTROUND=0 --- src/dynarec/arm64/dynarec_arm64_f30f.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/dynarec/arm64/dynarec_arm64_f30f.c b/src/dynarec/arm64/dynarec_arm64_f30f.c index 028ee7f4..ca5ef767 100755 --- a/src/dynarec/arm64/dynarec_arm64_f30f.c +++ b/src/dynarec/arm64/dynarec_arm64_f30f.c @@ -240,15 +240,15 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n case 0x5B: INST_NAME("CVTTPS2DQ Gx, Ex"); nextop = F8; - GETEX(d0, 0, 0) ; + GETEX(v1, 0, 0) ; GETGX_empty(v0); if(box64_dynarec_fastround) { - VFCVTZSQS(v0, d0); + VFCVTZSQS(v0, v1); } else { MRS_fpsr(x5); BFCw(x5, FPSR_IOC, 1); // reset IOC bit MSR_fpsr(x5); - MOV32w(x4, 0x80000000); + ORRw_mask(x4, xZR, 1, 0); //0x80000000 d0 = fpu_get_scratch(dyn); for(int i=0; i<4; ++i) { BFCw(x5, FPSR_IOC, 1); // reset IOC bit -- cgit 1.4.1