ucomiss 1.000000, 1.000000 => 0x242
ucomiss 1.000000, 2.000000 => 0x202
ucomiss 1.000000, 0.000000 => 0x203
ucomiss 1.000000, -0.000000 => 0x203
ucomiss 1.000000, -1.000000 => 0x203
ucomiss 1.000000, inf => 0x202
ucomiss 1.000000, -inf => 0x203
ucomiss 1.000000, nan => 0x247
ucomiss 2.000000, 1.000000 => 0x203
ucomiss 2.000000, 2.000000 => 0x242
ucomiss 2.000000, 0.000000 => 0x203
ucomiss 2.000000, -0.000000 => 0x203
ucomiss 2.000000, -1.000000 => 0x203
ucomiss 2.000000, inf => 0x202
ucomiss 2.000000, -inf => 0x203
ucomiss 2.000000, nan => 0x247
ucomiss 0.000000, 1.000000 => 0x202
ucomiss 0.000000, 2.000000 => 0x202
ucomiss 0.000000, 0.000000 => 0x242
ucomiss 0.000000, -0.000000 => 0x242
ucomiss 0.000000, -1.000000 => 0x203
ucomiss 0.000000, inf => 0x202
ucomiss 0.000000, -inf => 0x203
ucomiss 0.000000, nan => 0x247
ucomiss -0.000000, 1.000000 => 0x202
ucomiss -0.000000, 2.000000 => 0x202
ucomiss -0.000000, 0.000000 => 0x242
ucomiss -0.000000, -0.000000 => 0x242
ucomiss -0.000000, -1.000000 => 0x203
ucomiss -0.000000, inf => 0x202
ucomiss -0.000000, -inf => 0x203
ucomiss -0.000000, nan => 0x247
ucomiss -1.000000, 1.000000 => 0x202
ucomiss -1.000000, 2.000000 => 0x202
ucomiss -1.000000, 0.000000 => 0x202
ucomiss -1.000000, -0.000000 => 0x202
ucomiss -1.000000, -1.000000 => 0x242
ucomiss -1.000000, inf => 0x202
ucomiss -1.000000, -inf => 0x203
ucomiss -1.000000, nan => 0x247
ucomiss inf, 1.000000 => 0x203
ucomiss inf, 2.000000 => 0x203
ucomiss inf, 0.000000 => 0x203
ucomiss inf, -0.000000 => 0x203
ucomiss inf, -1.000000 => 0x203
ucomiss inf, inf => 0x242
ucomiss inf, -inf => 0x203
ucomiss inf, nan => 0x247
ucomiss -inf, 1.000000 => 0x202
ucomiss -inf, 2.000000 => 0x202
ucomiss -inf, 0.000000 => 0x202
ucomiss -inf, -0.000000 => 0x202
ucomiss -inf, -1.000000 => 0x202
ucomiss -inf, inf => 0x202
ucomiss -inf, -inf => 0x242
ucomiss -inf, nan => 0x247
ucomiss nan, 1.000000 => 0x247
ucomiss nan, 2.000000 => 0x247
ucomiss nan, 0.000000 => 0x247
ucomiss nan, -0.000000 => 0x247
ucomiss nan, -1.000000 => 0x247
ucomiss nan, inf => 0x247
ucomiss nan, -inf => 0x247
ucomiss nan, nan => 0x247
ucomisd 1.000000, 1.000000 => 0x242
ucomisd 1.000000, 2.000000 => 0x202
ucomisd 1.000000, 0.000000 => 0x203
ucomisd 1.000000, -0.000000 => 0x203
ucomisd 1.000000, -1.000000 => 0x203
ucomisd 1.000000, inf => 0x202
ucomisd 1.000000, -inf => 0x203
ucomisd 1.000000, nan => 0x247
ucomisd 2.000000, 1.000000 => 0x203
ucomisd 2.000000, 2.000000 => 0x242
ucomisd 2.000000, 0.000000 => 0x203
ucomisd 2.000000, -0.000000 => 0x203
ucomisd 2.000000, -1.000000 => 0x203
ucomisd 2.000000, inf => 0x202
ucomisd 2.000000, -inf => 0x203
ucomisd 2.000000, nan => 0x247
ucomisd 0.000000, 1.000000 => 0x202
ucomisd 0.000000, 2.000000 => 0x202
ucomisd 0.000000, 0.000000 => 0x242
ucomisd 0.000000, -0.000000 => 0x242
ucomisd 0.000000, -1.000000 => 0x203
ucomisd 0.000000, inf => 0x202
ucomisd 0.000000, -inf => 0x203
ucomisd 0.000000, nan => 0x247
ucomisd -0.000000, 1.000000 => 0x202
ucomisd -0.000000, 2.000000 => 0x202
ucomisd -0.000000, 0.000000 => 0x242
ucomisd -0.000000, -0.000000 => 0x242
ucomisd -0.000000, -1.000000 => 0x203
ucomisd -0.000000, inf => 0x202
ucomisd -0.000000, -inf => 0x203
ucomisd -0.000000, nan => 0x247
ucomisd -1.000000, 1.000000 => 0x202
ucomisd -1.000000, 2.000000 => 0x202
ucomisd -1.000000, 0.000000 => 0x202
ucomisd -1.000000, -0.000000 => 0x202
ucomisd -1.000000, -1.000000 => 0x242
ucomisd -1.000000, inf => 0x202
ucomisd -1.000000, -inf => 0x203
ucomisd -1.000000, nan => 0x247
ucomisd inf, 1.000000 => 0x203
ucomisd inf, 2.000000 => 0x203
ucomisd inf, 0.000000 => 0x203
ucomisd inf, -0.000000 => 0x203
ucomisd inf, -1.000000 => 0x203
ucomisd inf, inf => 0x242
ucomisd inf, -inf => 0x203
ucomisd inf, nan => 0x247
ucomisd -inf, 1.000000 => 0x202
ucomisd -inf, 2.000000 => 0x202
ucomisd -inf, 0.000000 => 0x202
ucomisd -inf, -0.000000 => 0x202
ucomisd -inf, -1.000000 => 0x202
ucomisd -inf, inf => 0x202
ucomisd -inf, -inf => 0x242
ucomisd -inf, nan => 0x247
ucomisd nan, 1.000000 => 0x247
ucomisd nan, 2.000000 => 0x247
ucomisd nan, 0.000000 => 0x247
ucomisd nan, -0.000000 => 0x247
ucomisd nan, -1.000000 => 0x247
ucomisd nan, inf => 0x247
ucomisd nan, -inf => 0x247
ucomisd nan, nan => 0x247
cmpsd 1.000000, 2.000000, 0 => 0x0
cmpsd 2.000000, 1.000000, 0 => 0x0
cmpsd 1.000000, inf, 0 => 0x0
cmpsd inf, 1.000000, 0 => 0x0
cmpsd 1.000000, -inf, 0 => 0x0
cmpsd -inf, 1.000000, 0 => 0x0
cmpsd 1.000000, nan, 0 => 0x0
cmpsd nan, 1.000000, 0 => 0x0
cmpsd 1.000000, 1.000000, 0 => 0xffffffffffffffff
cmpsd inf, inf, 0 => 0xffffffffffffffff
cmpsd nan, nan, 0 => 0x0
cmpsd 1.000000, 2.000000, 1 => 0xffffffffffffffff
cmpsd 2.000000, 1.000000, 1 => 0x0
cmpsd 1.000000, inf, 1 => 0xffffffffffffffff
cmpsd inf, 1.000000, 1 => 0x0
cmpsd 1.000000, -inf, 1 => 0x0
cmpsd -inf, 1.000000, 1 => 0xffffffffffffffff
cmpsd 1.000000, nan, 1 => 0x0
cmpsd nan, 1.000000, 1 => 0x0
cmpsd 1.000000, 1.000000, 1 => 0x0
cmpsd inf, inf, 1 => 0x0
cmpsd nan, nan, 1 => 0x0
cmpsd 1.000000, 2.000000, 2 => 0xffffffffffffffff
cmpsd 2.000000, 1.000000, 2 => 0x0
cmpsd 1.000000, inf, 2 => 0xffffffffffffffff
cmpsd inf, 1.000000, 2 => 0x0
cmpsd 1.000000, -inf, 2 => 0x0
cmpsd -inf, 1.000000, 2 => 0xffffffffffffffff
cmpsd 1.000000, nan, 2 => 0x0
cmpsd nan, 1.000000, 2 => 0x0
cmpsd 1.000000, 1.000000, 2 => 0xffffffffffffffff
cmpsd inf, inf, 2 => 0xffffffffffffffff
cmpsd nan, nan, 2 => 0x0
cmpsd 1.000000, 2.000000, 3 => 0x0
cmpsd 2.000000, 1.000000, 3 => 0x0
cmpsd 1.000000, inf, 3 => 0x0
cmpsd inf, 1.000000, 3 => 0x0
cmpsd 1.000000, -inf, 3 => 0x0
cmpsd -inf, 1.000000, 3 => 0x0
cmpsd 1.000000, nan, 3 => 0xffffffffffffffff
cmpsd nan, 1.000000, 3 => 0xffffffffffffffff
cmpsd 1.000000, 1.000000, 3 => 0x0
cmpsd inf, inf, 3 => 0x0
cmpsd nan, nan, 3 => 0xffffffffffffffff
cmpsd 1.000000, 2.000000, 4 => 0xffffffffffffffff
cmpsd 2.000000, 1.000000, 4 => 0xffffffffffffffff
cmpsd 1.000000, inf, 4 => 0xffffffffffffffff
cmpsd inf, 1.000000, 4 => 0xffffffffffffffff
cmpsd 1.000000, -inf, 4 => 0xffffffffffffffff
cmpsd -inf, 1.000000, 4 => 0xffffffffffffffff
cmpsd 1.000000, nan, 4 => 0xffffffffffffffff
cmpsd nan, 1.000000, 4 => 0xffffffffffffffff
cmpsd 1.000000, 1.000000, 4 => 0x0
cmpsd inf, inf, 4 => 0x0
cmpsd nan, nan, 4 => 0xffffffffffffffff
cmpsd 1.000000, 2.000000, 5 => 0x0
cmpsd 2.000000, 1.000000, 5 => 0xffffffffffffffff
cmpsd 1.000000, inf, 5 => 0x0
cmpsd inf, 1.000000, 5 => 0xffffffffffffffff
cmpsd 1.000000, -inf, 5 => 0xffffffffffffffff
cmpsd -inf, 1.000000, 5 => 0x0
cmpsd 1.000000, nan, 5 => 0xffffffffffffffff
cmpsd nan, 1.000000, 5 => 0xffffffffffffffff
cmpsd 1.000000, 1.000000, 5 => 0xffffffffffffffff
cmpsd inf, inf, 5 => 0xffffffffffffffff
cmpsd nan, nan, 5 => 0xffffffffffffffff
cmpsd 1.000000, 2.000000, 6 => 0x0
cmpsd 2.000000, 1.000000, 6 => 0xffffffffffffffff
cmpsd 1.000000, inf, 6 => 0x0
cmpsd inf, 1.000000, 6 => 0xffffffffffffffff
cmpsd 1.000000, -inf, 6 => 0xffffffffffffffff
cmpsd -inf, 1.000000, 6 => 0x0
cmpsd 1.000000, nan, 6 => 0xffffffffffffffff
cmpsd nan, 1.000000, 6 => 0xffffffffffffffff
cmpsd 1.000000, 1.000000, 6 => 0x0
cmpsd inf, inf, 6 => 0x0
cmpsd nan, nan, 6 => 0xffffffffffffffff
cmpsd 1.000000, 2.000000, 7 => 0xffffffffffffffff
cmpsd 2.000000, 1.000000, 7 => 0xffffffffffffffff
cmpsd 1.000000, inf, 7 => 0xffffffffffffffff
cmpsd inf, 1.000000, 7 => 0xffffffffffffffff
cmpsd 1.000000, -inf, 7 => 0xffffffffffffffff
cmpsd -inf, 1.000000, 7 => 0xffffffffffffffff
cmpsd 1.000000, nan, 7 => 0x0
cmpsd nan, 1.000000, 7 => 0x0
cmpsd 1.000000, 1.000000, 7 => 0xffffffffffffffff
cmpsd inf, inf, 7 => 0xffffffffffffffff
cmpsd nan, nan, 7 => 0x0
cvtsd2si 1.000000 => 0x1
cvtsd2si 1.490000 => 0x1
cvtsd2si 1.500000 => 0x2
cvtsd2si 1.510000 => 0x2
cvtsd2si -1.000000 => 0xffffffffffffffff
cvtsd2si -1.490000 => 0xffffffffffffffff
cvtsd2si -1.500000 => 0xfffffffffffffffe
cvtsd2si -1.510000 => 0xfffffffffffffffe
cvtsd2si 1e+300 => 0x8000000000000000
cvtsd2si -1e+300 => 0x8000000000000000
cvtsd2si inf => 0x8000000000000000
cvtsd2si -inf => 0x8000000000000000
cvtsd2si nan => 0x8000000000000000
cvtsd2si -0.000000 => 0x0
MMX RoundMode = 0
cvtsd2si 1.000000 => 0x1
cvtsd2si 1.490000 => 0x1
cvtsd2si 1.500000 => 0x2
cvtsd2si 1.510000 => 0x2
cvtsd2si -1.000000 => 0xffffffffffffffff
cvtsd2si -1.490000 => 0xffffffffffffffff
cvtsd2si -1.500000 => 0xfffffffffffffffe
cvtsd2si -1.510000 => 0xfffffffffffffffe
cvtsd2si 1e+300 => 0x8000000000000000
cvtsd2si -1e+300 => 0x8000000000000000
cvtsd2si inf => 0x8000000000000000
cvtsd2si -inf => 0x8000000000000000
cvtsd2si nan => 0x8000000000000000
cvtsd2si -0.000000 => 0x0
MMX RoundMode = 1
cvtsd2si 1.000000 => 0x1
cvtsd2si 1.490000 => 0x1
cvtsd2si 1.500000 => 0x1
cvtsd2si 1.510000 => 0x1
cvtsd2si -1.000000 => 0xffffffffffffffff
cvtsd2si -1.490000 => 0xfffffffffffffffe
cvtsd2si -1.500000 => 0xfffffffffffffffe
cvtsd2si -1.510000 => 0xfffffffffffffffe
cvtsd2si 1e+300 => 0x8000000000000000
cvtsd2si -1e+300 => 0x8000000000000000
cvtsd2si inf => 0x8000000000000000
cvtsd2si -inf => 0x8000000000000000
cvtsd2si nan => 0x8000000000000000
cvtsd2si -0.000000 => 0x0
MMX RoundMode = 2
cvtsd2si 1.000000 => 0x1
cvtsd2si 1.490000 => 0x2
cvtsd2si 1.500000 => 0x2
cvtsd2si 1.510000 => 0x2
cvtsd2si -1.000000 => 0xffffffffffffffff
cvtsd2si -1.490000 => 0xffffffffffffffff
cvtsd2si -1.500000 => 0xffffffffffffffff
cvtsd2si -1.510000 => 0xffffffffffffffff
cvtsd2si 1e+300 => 0x8000000000000000
cvtsd2si -1e+300 => 0x8000000000000000
cvtsd2si inf => 0x8000000000000000
cvtsd2si -inf => 0x8000000000000000
cvtsd2si nan => 0x8000000000000000
cvtsd2si -0.000000 => 0x0
MMX RoundMode = 3
cvtsd2si 1.000000 => 0x1
cvtsd2si 1.490000 => 0x1
cvtsd2si 1.500000 => 0x1
cvtsd2si 1.510000 => 0x1
cvtsd2si -1.000000 => 0xffffffffffffffff
cvtsd2si -1.490000 => 0xffffffffffffffff
cvtsd2si -1.500000 => 0xffffffffffffffff
cvtsd2si -1.510000 => 0xffffffffffffffff
cvtsd2si 1e+300 => 0x8000000000000000
cvtsd2si -1e+300 => 0x8000000000000000
cvtsd2si inf => 0x8000000000000000
cvtsd2si -inf => 0x8000000000000000
cvtsd2si nan => 0x8000000000000000
cvtsd2si -0.000000 => 0x0