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#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include <errno.h>
#include <signal.h>
#include <assert.h>
#include "debug.h"
#include "box64context.h"
#include "dynarec.h"
#include "emu/x64emu_private.h"
#include "emu/x64run_private.h"
#include "x64run.h"
#include "x64emu.h"
#include "box64stack.h"
#include "callback.h"
#include "bridge.h"
#include "emu/x64run_private.h"
#include "x64trace.h"
#include "dynarec_native.h"
#include "custommem.h"
#include "rv64_printer.h"
#include "dynarec_rv64_private.h"
#include "dynarec_rv64_functions.h"
#include "dynarec_rv64_helper.h"
int isSimpleWrapper(wrapper_t fun);
uintptr_t dynarec64_00_1(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
{
uint8_t nextop, opcode;
uint8_t gd, ed;
int8_t i8;
int32_t i32, tmp;
int64_t i64, j64;
uint8_t u8;
uint8_t gb1, gb2, eb1, eb2;
uint32_t u32;
uint64_t u64;
uint8_t wback, wb1, wb2, wb;
int64_t fixedaddress;
int lock;
int cacheupd = 0;
opcode = F8;
MAYUSE(eb1);
MAYUSE(eb2);
MAYUSE(j64);
MAYUSE(wb);
MAYUSE(lock);
MAYUSE(cacheupd);
switch(opcode) {
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x44:
case 0x45:
case 0x46:
case 0x47:
INST_NAME("INC Reg (32bits)");
SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
gd = xRAX + (opcode&7);
emit_inc32(dyn, ninst, rex, gd, x1, x2, x3, x4);
break;
case 0x48:
case 0x49:
case 0x4A:
case 0x4B:
case 0x4C:
case 0x4D:
case 0x4E:
case 0x4F:
INST_NAME("DEC Reg (32bits)");
SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
gd = xRAX + (opcode&7);
emit_dec32(dyn, ninst, rex, gd, x1, x2, x3, x4);
break;
case 0x50:
case 0x51:
case 0x52:
case 0x53:
case 0x54:
case 0x55:
case 0x56:
case 0x57:
INST_NAME("PUSH reg");
gd = xRAX+(opcode&0x07)+(rex.b<<3);
PUSH1z(gd);
break;
case 0x58:
case 0x59:
case 0x5A:
case 0x5B:
case 0x5C:
case 0x5D:
case 0x5E:
case 0x5F:
INST_NAME("POP reg");
gd = xRAX+(opcode&0x07)+(rex.b<<3);
POP1z(gd);
break;
case 0x60:
if(rex.is32bits) {
INST_NAME("PUSHAD");
AND(x1, xRSP, xMASK);
PUSH1_32(xRAX);
PUSH1_32(xRCX);
PUSH1_32(xRDX);
PUSH1_32(xRBX);
PUSH1_32(x1);
PUSH1_32(xRBP);
PUSH1_32(xRSI);
PUSH1_32(xRDI);
} else {
DEFAULT;
}
break;
case 0x61:
if(rex.is32bits) {
INST_NAME("POPAD");
POP1_32(xRDI);
POP1_32(xRSI);
POP1_32(xRBP);
POP1_32(x1);
POP1_32(xRBX);
POP1_32(xRDX);
POP1_32(xRCX);
POP1_32(xRAX);
} else {
DEFAULT;
}
break;
case 0x63:
if(rex.is32bits) {
// this is ARPL opcode
DEFAULT;
} else {
INST_NAME("MOVSXD Gd, Ed");
nextop = F8;
GETGD;
if(rex.w) {
if(MODREG) { // reg <= reg
ADDIW(gd, xRAX+(nextop&7)+(rex.b<<3), 0);
} else { // mem <= reg
SMREAD();
addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
LW(gd, ed, fixedaddress);
}
} else {
if(MODREG) { // reg <= reg
AND(gd, xRAX+(nextop&7)+(rex.b<<3), xMASK);
} else { // mem <= reg
SMREAD();
addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
LWU(gd, ed, fixedaddress);
}
}
}
break;
case 0x64:
addr = dynarec64_64(dyn, addr, ip, ninst, rex, rep, _FS, ok, need_epilog);
break;
case 0x65:
addr = dynarec64_64(dyn, addr, ip, ninst, rex, rep, _GS, ok, need_epilog);
break;
case 0x66:
addr = dynarec64_66(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
break;
case 0x67:
if(rex.is32bits)
addr = dynarec64_67_32(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
else
addr = dynarec64_67(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
break;
case 0x68:
INST_NAME("PUSH Id");
i64 = F32S;
if(PK(0)==0xC3) {
MESSAGE(LOG_DUMP, "PUSH then RET, using indirect\n");
TABLE64(x3, addr-4);
LW(x1, x3, 0);
PUSH1z(x1);
} else {
MOV64z(x3, i64);
PUSH1z(x3);
}
break;
case 0x69:
INST_NAME("IMUL Gd, Ed, Id");
SETFLAGS(X_ALL, SF_PENDING);
nextop = F8;
GETGD;
GETED(4);
i64 = F32S;
MOV64xw(x4, i64);
if(rex.w) {
// 64bits imul
UFLAG_IF {
MULH(x3, ed, x4);
MUL(gd, ed, x4);
UFLAG_OP1(x3);
UFLAG_RES(gd);
UFLAG_DF(x3, d_imul64);
} else {
MULxw(gd, ed, x4);
}
} else {
// 32bits imul
UFLAG_IF {
SEXT_W(x3, ed);
MUL(gd, x3, x4);
UFLAG_RES(gd);
SRLI(x3, gd, 32);
UFLAG_OP1(x3);
UFLAG_DF(x3, d_imul32);
} else {
MULxw(gd, ed, x4);
}
ZEROUP(gd);
}
break;
case 0x6A:
INST_NAME("PUSH Ib");
i64 = F8S;
MOV64z(x3, i64);
PUSH1z(x3);
break;
case 0x6B:
INST_NAME("IMUL Gd, Ed, Ib");
SETFLAGS(X_ALL, SF_PENDING);
nextop = F8;
GETGD;
GETED(1);
i64 = F8S;
MOV64xw(x4, i64);
if(rex.w) {
// 64bits imul
UFLAG_IF {
MULH(x3, ed, x4);
MUL(gd, ed, x4);
UFLAG_OP1(x3);
UFLAG_RES(gd);
UFLAG_DF(x3, d_imul64);
} else {
MUL(gd, ed, x4);
}
} else {
// 32bits imul
UFLAG_IF {
SEXT_W(x3, ed);
MUL(gd, x3, x4);
UFLAG_RES(gd);
SRLI(x3, gd, 32);
UFLAG_OP1(x3);
UFLAG_DF(x3, d_imul32);
} else {
MULW(gd, ed, x4);
}
ZEROUP(gd);
}
break;
case 0x6C:
case 0x6D:
INST_NAME(opcode == 0x6C ? "INSB" : "INSD");
SETFLAGS(X_ALL, SF_SET_NODF); // Hack to set flags in "don't care" state
GETIP(ip);
STORE_XEMU_CALL(x3);
CALL(native_priv, -1);
LOAD_XEMU_CALL();
jump_to_epilog(dyn, 0, xRIP, ninst);
*need_epilog = 0;
*ok = 0;
break;
case 0x6E:
case 0x6F:
INST_NAME(opcode == 0x6C ? "OUTSB" : "OUTSD");
SETFLAGS(X_ALL, SF_SET_NODF); // Hack to set flags in "don't care" state
GETIP(ip);
STORE_XEMU_CALL(x3);
CALL(native_priv, -1);
LOAD_XEMU_CALL();
jump_to_epilog(dyn, 0, xRIP, ninst);
*need_epilog = 0;
*ok = 0;
break;
#define GO(GETFLAGS, NO, YES, F) \
if (box64_dynarec_test == 2) { NOTEST(x1); } \
READFLAGS(F); \
i8 = F8S; \
BARRIER(BARRIER_MAYBE); \
JUMP(addr+i8, 1); \
GETFLAGS; \
if(dyn->insts[ninst].x64.jmp_insts==-1 || \
CHECK_CACHE()) { \
/* out of the block */ \
i32 = dyn->insts[ninst].epilog-(dyn->native_size); \
B##NO##_safe(x1, i32); \
if(dyn->insts[ninst].x64.jmp_insts==-1) { \
if(!(dyn->insts[ninst].x64.barrier&BARRIER_FLOAT)) \
fpu_purgecache(dyn, ninst, 1, x1, x2, x3); \
jump_to_next(dyn, addr+i8, 0, ninst, rex.is32bits); \
} else { \
CacheTransform(dyn, ninst, cacheupd, x1, x2, x3); \
i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);\
B(i32); \
} \
} else { \
/* inside the block */ \
i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size); \
B##YES##_safe(x1, i32); \
}
GOCOND(0x70, "J", "ib");
#undef GO
default:
DEFAULT;
}
return addr;
}
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