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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-05-21 21:21:26 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-05-21 21:21:26 +0200 |
| commit | 4b927bc37359dec23f67d3427fc982945f24f404 (patch) | |
| tree | 245449ef9146942dc7fffd0235b48b7e70a00bf2 /gitlab/issues/target_i386/host_missing/accel_missing/1164.toml | |
| parent | aa8bd79cec7bf6790ddb01d156c2ef2201abbaab (diff) | |
| download | emulator-bug-study-4b927bc37359dec23f67d3427fc982945f24f404.tar.gz emulator-bug-study-4b927bc37359dec23f67d3427fc982945f24f404.zip | |
add gitlab issues in toml format
Diffstat (limited to 'gitlab/issues/target_i386/host_missing/accel_missing/1164.toml')
| -rw-r--r-- | gitlab/issues/target_i386/host_missing/accel_missing/1164.toml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/gitlab/issues/target_i386/host_missing/accel_missing/1164.toml b/gitlab/issues/target_i386/host_missing/accel_missing/1164.toml new file mode 100644 index 00000000..bfc16389 --- /dev/null +++ b/gitlab/issues/target_i386/host_missing/accel_missing/1164.toml @@ -0,0 +1,27 @@ +id = 1164 +title = "q35: incorrect values for PCIEXBAR masks" +state = "opened" +created_at = "2022-08-18T02:46:56.030Z" +closed_at = "n/a" +labels = ["device: PCI", "target: i386"] +url = "https://gitlab.com/qemu-project/qemu/-/issues/1164" +host-os = "n/a" +host-arch = "n/a" +qemu-version = "n/a" +guest-os = "n/a" +guest-arch = "n/a" +description = """https://lore.kernel.org/all/1fded151ce5ecbf7010427871b908000b2aba9ee.1520867956.git.x1917x@gmail.com/ + +In function [mch_update_pciexbar](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/pci-host/q35.c#L295) + +There are two small issues in PCIEXBAR address mask handling: +- wrong bit positions for address mask bits (see PCIEXBAR description + in Q35 datasheet) +- incorrect usage of 64ADR_MASK + +Due to this, attempting to write a valid PCIEXBAR address may cause it to +shift to another address, causing memory layout corruption where emulated +MMIO regions may overlap real (passed through) MMIO ranges. Fix this +by providing correct values.""" +reproduce = "n/a" +additional = """Q35 datasheet: https://www.intel.com/Assets/PDF/datasheet/316966.pdf ( 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address )""" |