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Diffstat (limited to 'results/classifier/105/graphic/2571')
| -rw-r--r-- | results/classifier/105/graphic/2571 | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/results/classifier/105/graphic/2571 b/results/classifier/105/graphic/2571 new file mode 100644 index 00000000..419bcde1 --- /dev/null +++ b/results/classifier/105/graphic/2571 @@ -0,0 +1,79 @@ +mistranslation: 0.926 +graphic: 0.926 +other: 0.923 +semantic: 0.917 +instruction: 0.912 +boot: 0.903 +device: 0.902 +assembly: 0.898 +KVM: 0.859 +socket: 0.849 +vnc: 0.804 +network: 0.795 + +9.1.0 spurious guest journal errors -> linux guest on AMD host +Description of problem: +Since upgrading to 9.1.0 I'm seeing new error messages (see below) inside the guest when booting linux guests on an AMD host. Bisection points to: +``` +2ba8b7ee63589d4063c3b8dff3b70dbf9e224fc6 is the first bad commit +commit 2ba8b7ee63589d4063c3b8dff3b70dbf9e224fc6 +Author: John Allen <john.allen@amd.com> +Date: Mon Jun 3 19:36:21 2024 +0000 + + i386: Add support for SUCCOR feature + + Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required to + be exposed to guests to allow them to handle machine check exceptions on AMD + hosts. +``` +Everything still seems to work so possibly not a bug. But the errors are still very disconcerting. Any thoughts? +Steps to reproduce: +1. e.g. Boot linux with `-cpu host` on an AMD host +Additional information: +``` +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: unchecked MSR access error: RDMSR from 0x852 at rIP: 0xffffffffb548ffa7 (native_read_msr+0x7/0x40) +Sep 14 12:02:53 kernel: Call Trace: +Sep 14 12:02:53 kernel: <TASK> +Sep 14 12:02:53 kernel: ? ex_handler_msr.isra.0.cold+0x28/0x60 +Sep 14 12:02:53 kernel: ? fixup_exception+0x157/0x380 +Sep 14 12:02:53 kernel: ? gp_try_fixup_and_notify+0x1e/0xb0 +Sep 14 12:02:53 kernel: ? exc_general_protection+0x104/0x400 +Sep 14 12:02:53 kernel: ? asm_exc_general_protection+0x26/0x30 +Sep 14 12:02:53 kernel: ? native_read_msr+0x7/0x40 +Sep 14 12:02:53 kernel: native_apic_msr_read+0x20/0x30 +Sep 14 12:02:53 kernel: setup_APIC_eilvt+0x47/0x110 +Sep 14 12:02:53 kernel: mce_amd_feature_init+0x485/0x4e0 +Sep 14 12:02:53 kernel: mcheck_cpu_init+0x1bb/0x470 +Sep 14 12:02:53 kernel: identify_cpu+0x396/0x5e0 +Sep 14 12:02:53 kernel: arch_cpu_finalize_init+0x20/0x140 +Sep 14 12:02:53 kernel: start_kernel+0x931/0x9c0 +Sep 14 12:02:53 kernel: x86_64_start_reservations+0x24/0x30 +Sep 14 12:02:53 kernel: x86_64_start_kernel+0x95/0xa0 +Sep 14 12:02:53 kernel: common_startup_64+0x13e/0x141 +Sep 14 12:02:53 kernel: </TASK> +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 0, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 2, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 4, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 6, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: #1 #3 #5 #7 +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 1, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 3, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 5, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +Sep 14 12:02:53 kernel: mce: [Firmware Bug]: Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly. +Sep 14 12:02:53 kernel: [Firmware Bug]: cpu 7, try to use APIC520 (LVT offset 2) for vector 0xf4, but the register is already in use for vector 0x +0 on this cpu +``` |