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Diffstat (limited to 'results/classifier/108/other/1862167')
| -rw-r--r-- | results/classifier/108/other/1862167 | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/results/classifier/108/other/1862167 b/results/classifier/108/other/1862167 new file mode 100644 index 00000000..93e49505 --- /dev/null +++ b/results/classifier/108/other/1862167 @@ -0,0 +1,34 @@ +graphic: 0.779 +performance: 0.718 +device: 0.706 +other: 0.701 +semantic: 0.633 +vnc: 0.621 +network: 0.540 +PID: 0.448 +permissions: 0.438 +socket: 0.431 +files: 0.399 +KVM: 0.390 +boot: 0.382 +debug: 0.339 + +Variation of SVE register size (qemu-user-aarch64) + +Specification of ARMv8-A SVE extention allows various values for the size of the SVE register. On the other hand, it seems that the current qemu-aarch64 supports only the maximum length of 2048 bits as the SVE register size. I am writing an assembler program for a CPU that is compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when this is run with qemu-user-aarch64, a 2048-bit load / store instruction is executed This causes a segmentation fault. Shouldn't qeum-user-aarch64 have an option to specify the SVE register size? + +This is already managed by a cpu property. + +0df9142d27d5 ("target/arm/cpu64: max cpu: Introduce sve<N> properties") + +See docs/arm-cpu-features.rst + +Try "-cpu max,sve512=on". + + + +Note also that the vector length in SVE is not fixed -- you should be writing your guest code to support arbitrary vector lengths, because otherwise it will not run on all SVE-supporting CPUs. + + +Thank you for your kind advice. I'll try it. + |