1 files changed, 98 insertions, 0 deletions
diff --git a/results/classifier/118/mistranslation-ppc/608107 b/results/classifier/118/mistranslation-ppc/608107
new file mode 100644
index 00000000..b776f764
--- /dev/null
+++ b/results/classifier/118/mistranslation-ppc/608107
@@ -0,0 +1,98 @@
+ppc: 0.970
+mistranslation: 0.851
+PID: 0.819
+kernel: 0.760
+architecture: 0.746
+device: 0.708
+semantic: 0.703
+files: 0.697
+register: 0.662
+socket: 0.659
+performance: 0.647
+hypervisor: 0.603
+user-level: 0.596
+risc-v: 0.555
+network: 0.554
+vnc: 0.546
+permissions: 0.537
+assembly: 0.525
+boot: 0.515
+graphic: 0.501
+arm: 0.494
+x86: 0.432
+VMM: 0.418
+KVM: 0.395
+debug: 0.383
+peripherals: 0.382
+i386: 0.351
+TCG: 0.348
+virtual: 0.296
+--------------------
+ppc: 0.963
+architecture: 0.348
+performance: 0.092
+semantic: 0.089
+debug: 0.088
+files: 0.059
+register: 0.037
+network: 0.028
+hypervisor: 0.020
+virtual: 0.020
+PID: 0.018
+device: 0.013
+boot: 0.011
+TCG: 0.010
+socket: 0.009
+kernel: 0.008
+vnc: 0.007
+assembly: 0.006
+user-level: 0.004
+peripherals: 0.004
+risc-v: 0.004
+permissions: 0.002
+mistranslation: 0.002
+VMM: 0.002
+graphic: 0.002
+x86: 0.001
+arm: 0.001
+KVM: 0.001
+i386: 0.000
+
+ppc fails to clear MSR_POW when incurring exception
+
+QEMU VERSION: 0.12.4
+
+According to FreeScale's 'Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005], section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4 fails to do so.
+Resetting the bit is necessary in order to bring the processor out of power-management since otherwise it goes to sleep right away in the exception handler, i.e., it is impossible to leave PM-mode.
+
+
+
+Thomas Monjalon wrote:
+> From: till <email address hidden>
+>
+> According to FreeScale's 'Programming Environments Manual for 32-bit
+> Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005],
+> section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4
+> fails to do so.
+> Resetting the bit is necessary in order to bring the processor out of power
+> management since otherwise it goes to sleep right away in the exception
+> handler, i.e., it is impossible to leave PM-mode.
+>   
+
+This doesn't look right. POW shouldn't even get stored in SRR1. Could
+you please redo the patch and make sure that mtmsr masks out MSR_POW?
+
+
+Alex
+
+
+I'm afraid I don't understand. My the problem and fix doesn't address mtmsr at all.
+It just makes sure MSR_POW is cleared in MSR when an exception occurs.
+
+Do you mean MSR_POW should masked from MSR before saving it to SRR1?
+That's already taken care of (target-ppc/helper.c:2074 [qemu-0.12.4]).
+
+As far as I can see, this problem has been fixed by this commit here:
+http://git.qemu.org/?p=qemu.git;a=commitdiff;h=41557447d30eeb944e4
+... so I'm setting the status to "Fix released" now.
+