diff options
Diffstat (limited to 'results/classifier/deepseek-2-tmp/output/mistranslation/1574346')
| -rw-r--r-- | results/classifier/deepseek-2-tmp/output/mistranslation/1574346 | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/results/classifier/deepseek-2-tmp/output/mistranslation/1574346 b/results/classifier/deepseek-2-tmp/output/mistranslation/1574346 deleted file mode 100644 index 01f55e51..00000000 --- a/results/classifier/deepseek-2-tmp/output/mistranslation/1574346 +++ /dev/null @@ -1,13 +0,0 @@ - -TCG: mov to segment register is incorrectly emulated for AMD CPUs - -In TCG mode, the effect of: - -xorl %eax, %eax -movl %eax, %gs - -is to mark the GS segment unusable and set its base to zero. After doing this, reading MSR_GS_BASE will return zero and using a GS prefix in long mode will treat the GS base as zero. - -This is correct for Intel CPUs but is incorrect for AMD CPUs. On an AMD CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave the base unchanged. - -To make it easier to use TCG to validate behavior on different CPUs, please consider changing the TCG behavior to match actual CPU behavior when emulating an AMD CPU. \ No newline at end of file |