diff options
Diffstat (limited to '')
| -rw-r--r-- | results/classifier/gemma3:12b/assembly/241 | 2 | ||||
| -rw-r--r-- | results/classifier/gemma3:12b/assembly/2413 | 34 | ||||
| -rw-r--r-- | results/classifier/gemma3:12b/assembly/2419 | 19 |
3 files changed, 55 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/assembly/241 b/results/classifier/gemma3:12b/assembly/241 new file mode 100644 index 00000000..ae4b719b --- /dev/null +++ b/results/classifier/gemma3:12b/assembly/241 @@ -0,0 +1,2 @@ + +Please refactor linux-user/mips/cpu_loop.c diff --git a/results/classifier/gemma3:12b/assembly/2413 b/results/classifier/gemma3:12b/assembly/2413 new file mode 100644 index 00000000..97b903ce --- /dev/null +++ b/results/classifier/gemma3:12b/assembly/2413 @@ -0,0 +1,34 @@ + +Use of TSTEQ/TSTNE has regressed the cdrom test when running a 32 bit build of qemu-system-x86_64 using TCG +Description of problem: +The test freezes, eventually timing out. The bisect was confused by other SEV related things so I had to whittle down the config to --disable-kvm. +Steps to reproduce: +1. '../../configure' '--disable-docs' '--disable-user' '--cross-prefix=i686-linux-gnu-' '--target-list=x86_64-softmmu' '--enable-debug' '--disable-kvm' +2. ninja +3. meson test -t 0.05 qtest-x86_64/cdrom-test V=1 +Additional information: +Bisect run pointed at: + +``` +commit 15957eb9efe2da67c796612cead95cba28ba9bda +Author: Paolo Bonzini <pbonzini@redhat.com> +Date: Fri Oct 27 05:57:31 2023 +0200 + + target/i386: use TSTEQ/TSTNE to test low bits + + When testing the sign bit or equality to zero of a partial register, it + is useful to use a single TSTEQ or TSTNE operation. It can also be used + to test the parity flag, using bit 0 of the population count. + + Do not do this for target_ulong-sized values however; the optimizer would + produce a comparison against zero anyway, and it avoids shifts by 64 + which are undefined behavior. + + Reviewed-by: Richard Henderson <richard.henderson@linaro.org> + Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> + + target/i386/tcg/translate.c | 28 ++++++++++++++++++++-------- + target/i386/tcg/emit.c.inc | 5 ++--- + 2 files changed, 22 insertions(+), 11 deletions(-) +bisect found first bad commitâ +``` diff --git a/results/classifier/gemma3:12b/assembly/2419 b/results/classifier/gemma3:12b/assembly/2419 new file mode 100644 index 00000000..90c425b4 --- /dev/null +++ b/results/classifier/gemma3:12b/assembly/2419 @@ -0,0 +1,19 @@ + +ldapr_stlr_i instructions doesn't consider signed offset +Description of problem: +The format ldapr_stlr_i models the load acquire / store release immediate instructions. \ +These instructions has a bug in the sign extension calculation of the imm field. \ +imm should be defined as s9 instead of 9. + +@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i + +Should be changed to: + +@ldapr_stlr_i .. ...... .. . imm:s9 .. rn:5 rt:5 &ldapr_stlr_i +Steps to reproduce: +1. Run ARM target +2. Generate any ldapr_stlr_i instructions (for example: LDAPUR) +3. When the imm value is negative, the immediate calculation is done wrong. In case the calculation leads to an undefined location, QEMU will fail. +Additional information: +In trans_LDAPR_i (translate-a64.c), when imm field is negative, the value of a->imm will be 512-x instead of x. \ +I already fixed the issue by adding the s9 to the imm field. This made a call to sextend32 for imm instead of extend32 in the generated file build/libqemu-aarch64-softmmu.fa.p/decode-a64.c.inc |