diff options
Diffstat (limited to '')
| -rw-r--r-- | results/classifier/gemma3:12b/device/116 | 2 | ||||
| -rw-r--r-- | results/classifier/gemma3:12b/device/1161 | 2 | ||||
| -rw-r--r-- | results/classifier/gemma3:12b/device/1164 | 18 |
3 files changed, 22 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/device/116 b/results/classifier/gemma3:12b/device/116 new file mode 100644 index 00000000..78dda4b9 --- /dev/null +++ b/results/classifier/gemma3:12b/device/116 @@ -0,0 +1,2 @@ + +qemu fails under NeXTStep 3.3 when accessing ROM in SCSI-Adapter am53c974 diff --git a/results/classifier/gemma3:12b/device/1161 b/results/classifier/gemma3:12b/device/1161 new file mode 100644 index 00000000..cde2c7f2 --- /dev/null +++ b/results/classifier/gemma3:12b/device/1161 @@ -0,0 +1,2 @@ + +revise docs/interop/virtio-balloon-stats.rst diff --git a/results/classifier/gemma3:12b/device/1164 b/results/classifier/gemma3:12b/device/1164 new file mode 100644 index 00000000..4f7b5d91 --- /dev/null +++ b/results/classifier/gemma3:12b/device/1164 @@ -0,0 +1,18 @@ + +q35: incorrect values for PCIEXBAR masks +Description of problem: +https://lore.kernel.org/all/1fded151ce5ecbf7010427871b908000b2aba9ee.1520867956.git.x1917x@gmail.com/ + +In function [mch_update_pciexbar](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/pci-host/q35.c#L295) + +There are two small issues in PCIEXBAR address mask handling: +- wrong bit positions for address mask bits (see PCIEXBAR description + in Q35 datasheet) +- incorrect usage of 64ADR_MASK + +Due to this, attempting to write a valid PCIEXBAR address may cause it to +shift to another address, causing memory layout corruption where emulated +MMIO regions may overlap real (passed through) MMIO ranges. Fix this +by providing correct values. +Additional information: +Q35 datasheet: https://www.intel.com/Assets/PDF/datasheet/316966.pdf ( 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ) |