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Diffstat (limited to '')
| -rw-r--r-- | results/classifier/gemma3:12b/device/424450 | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/device/424450 b/results/classifier/gemma3:12b/device/424450 new file mode 100644 index 00000000..4b650fe9 --- /dev/null +++ b/results/classifier/gemma3:12b/device/424450 @@ -0,0 +1,15 @@ + +FDC reset should reset the MSR + +I believe that the MSR resgister should also be reset to zero on a software reset. All of the FDC hardware I have does this. +The current code leaves the MSR as 0x80, which means that the controller is ready for a write. The controller should not +be ready for a write while in reset. + +fdc.c Line 899 + /* Reset */ + if (!(value & FD_DOR_nRESET)) { + + fdctrl->msr = 0x00; + if (fdctrl->dor & FD_DOR_nRESET) { + FLOPPY_DPRINTF("controller enter RESET state\n"); + } + } else {
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