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Diffstat (limited to 'results/classifier/phi4:14b/output/manual-review/1574346')
| -rw-r--r-- | results/classifier/phi4:14b/output/manual-review/1574346 | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/results/classifier/phi4:14b/output/manual-review/1574346 b/results/classifier/phi4:14b/output/manual-review/1574346 new file mode 100644 index 00000000..59fce0e2 --- /dev/null +++ b/results/classifier/phi4:14b/output/manual-review/1574346 @@ -0,0 +1,15 @@ + + + +TCG: mov to segment register is incorrectly emulated for AMD CPUs + +In TCG mode, the effect of: + +xorl %eax, %eax +movl %eax, %gs + +is to mark the GS segment unusable and set its base to zero. After doing this, reading MSR_GS_BASE will return zero and using a GS prefix in long mode will treat the GS base as zero. + +This is correct for Intel CPUs but is incorrect for AMD CPUs. On an AMD CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave the base unchanged. + +To make it easier to use TCG to validate behavior on different CPUs, please consider changing the TCG behavior to match actual CPU behavior when emulating an AMD CPU. \ No newline at end of file |