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Diffstat (limited to 'results/classifier/phi4:14b/output/manual-review/1862167')
| -rw-r--r-- | results/classifier/phi4:14b/output/manual-review/1862167 | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/results/classifier/phi4:14b/output/manual-review/1862167 b/results/classifier/phi4:14b/output/manual-review/1862167 new file mode 100644 index 00000000..512a54b7 --- /dev/null +++ b/results/classifier/phi4:14b/output/manual-review/1862167 @@ -0,0 +1,6 @@ + + + +Variation of SVE register size (qemu-user-aarch64) + +Specification of ARMv8-A SVE extention allows various values for the size of the SVE register. On the other hand, it seems that the current qemu-aarch64 supports only the maximum length of 2048 bits as the SVE register size. I am writing an assembler program for a CPU that is compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when this is run with qemu-user-aarch64, a 2048-bit load / store instruction is executed This causes a segmentation fault. Shouldn't qeum-user-aarch64 have an option to specify the SVE register size? \ No newline at end of file |