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Diffstat (limited to 'results/classifier/qwen3:32b/reasoning/instruction/2317')
| -rw-r--r-- | results/classifier/qwen3:32b/reasoning/instruction/2317 | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/results/classifier/qwen3:32b/reasoning/instruction/2317 b/results/classifier/qwen3:32b/reasoning/instruction/2317 new file mode 100644 index 00000000..014f29ee --- /dev/null +++ b/results/classifier/qwen3:32b/reasoning/instruction/2317 @@ -0,0 +1,13 @@ +<think> +Okay, let's see. The user is reporting a bug in QEMU related to the SH4 architecture's ADDV instruction. The problem is that the ADDV opcode isn't being emulated correctly. + +The description says that according to the documentation, ADDV Rm, Rn should add Rn and Rm, store the result in Rn, and set the T flag on overflow. But QEMU is doing Rn + Rm and storing the result in Rm instead, which is the opposite of what it should be. + +The steps to reproduce include a C program that uses inline assembly. On real hardware, the output shows that 'a' (r8) becomes 0x80000000, which is the correct result of adding 0x7fffffff and 1. However, in QEMU, 'a' remains 0x7fffffff and 'b' (r9) becomes 0x80000000. That suggests that QEMU is writing the result to Rm (r9) instead of Rn (r8). + +The key here is the instruction's operand order. The ADDV instruction's syntax is ADDV Rm, Rn. The first operand is Rm, the second is Rn. The correct behavior is Rn = Rn + Rm, but QEMU is doing Rm = Rn + Rm. So the emulation is swapping the destination register. + +This is definitely an issue with the instruction emulation. The QEMU code for SH4's ADDV is not following the documented behavior. The problem isn't with a syscall or runtime environment; it's specifically about how the ADDV instruction is handled. So the category should be 'instruction'. +</think> + +instruction \ No newline at end of file |