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Diffstat (limited to 'results/classifier/qwen3:32b/reasoning/instruction/2595')
| -rw-r--r-- | results/classifier/qwen3:32b/reasoning/instruction/2595 | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/results/classifier/qwen3:32b/reasoning/instruction/2595 b/results/classifier/qwen3:32b/reasoning/instruction/2595 new file mode 100644 index 00000000..2fc96bd8 --- /dev/null +++ b/results/classifier/qwen3:32b/reasoning/instruction/2595 @@ -0,0 +1,11 @@ +<think> +Okay, let's try to figure out how to classify this bug report. The user says the problem is with the SDOT and UDOT instructions on ARM SVE when using QEMU with certain vector lengths. They tested it with the Arm Instruction Emulator and gem5, which gave correct results, but QEMU is producing incorrect outputs. + +First, the issue is related to specific CPU instructions (SDOT and UDOT) in QEMU. The problem occurs when the vector length is 64 or higher. The user provided a test case that compiles with specific flags and runs under QEMU with different SVE vector lengths. The output discrepancies start appearing at 64 and above. + +Looking at the categories: instruction, syscall, runtime. + +The bug is about the incorrect execution of specific instructions (SDOT/UDOT) in QEMU. Since QEMU is the emulator here, and the instructions are not being handled properly, this would fall under the "instruction" category. The problem isn't with a system call or runtime environment but with how QEMU implements those particular instructions. The user even mentions that the generated assembly uses the correct intrinsics, so the issue is in QEMU's execution of those instructions. Therefore, it's an instruction-related bug in QEMU. +</think> + +instruction \ No newline at end of file |