From 4b927bc37359dec23f67d3427fc982945f24f404 Mon Sep 17 00:00:00 2001 From: Christian Krinitsin Date: Wed, 21 May 2025 21:21:26 +0200 Subject: add gitlab issues in toml format --- .../host_missing/accel_missing/2931.toml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 gitlab/issues/target_missing/host_missing/accel_missing/2931.toml (limited to 'gitlab/issues/target_missing/host_missing/accel_missing/2931.toml') diff --git a/gitlab/issues/target_missing/host_missing/accel_missing/2931.toml b/gitlab/issues/target_missing/host_missing/accel_missing/2931.toml new file mode 100644 index 00000000..17bbabcf --- /dev/null +++ b/gitlab/issues/target_missing/host_missing/accel_missing/2931.toml @@ -0,0 +1,36 @@ +id = 2931 +title = "riscv: satp invalid while kvm set to cpu host" +state = "opened" +created_at = "2025-04-25T08:43:40.505Z" +closed_at = "n/a" +labels = [] +url = "https://gitlab.com/qemu-project/qemu/-/issues/2931" +host-os = "Linux" +host-arch = "riscv64" +qemu-version = "any (master)" +guest-os = "Any" +guest-arch = "riscv64" +description = """After boot, no "mmu-type" in dtb +``` + cpu@0 { + + phandle = <0x7>; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + compatible = "riscv"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zi +bb"; + riscv,isa-base = "rv64i"; + riscv,isa = "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zba_zbb"; + interrupt-controller { + + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x8>; + }; + }; +```""" +reproduce = """1. boot any qemu with `-cpu host`""" +additional = "n/a" -- cgit 1.4.1