From d0c85e36e4de67af628d54e9ab577cc3fad7796a Mon Sep 17 00:00:00 2001 From: Christian Krinitsin Date: Thu, 3 Jul 2025 07:27:52 +0000 Subject: add deepseek and gemma results --- results/classifier/gemma3:12b/hypervisor/1574346 | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 results/classifier/gemma3:12b/hypervisor/1574346 (limited to 'results/classifier/gemma3:12b/hypervisor/1574346') diff --git a/results/classifier/gemma3:12b/hypervisor/1574346 b/results/classifier/gemma3:12b/hypervisor/1574346 new file mode 100644 index 00000000..01f55e51 --- /dev/null +++ b/results/classifier/gemma3:12b/hypervisor/1574346 @@ -0,0 +1,13 @@ + +TCG: mov to segment register is incorrectly emulated for AMD CPUs + +In TCG mode, the effect of: + +xorl %eax, %eax +movl %eax, %gs + +is to mark the GS segment unusable and set its base to zero. After doing this, reading MSR_GS_BASE will return zero and using a GS prefix in long mode will treat the GS base as zero. + +This is correct for Intel CPUs but is incorrect for AMD CPUs. On an AMD CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave the base unchanged. + +To make it easier to use TCG to validate behavior on different CPUs, please consider changing the TCG behavior to match actual CPU behavior when emulating an AMD CPU. \ No newline at end of file -- cgit 1.4.1