other: 0.742 debug: 0.729 semantic: 0.658 performance: 0.607 device: 0.596 graphic: 0.384 vnc: 0.359 network: 0.346 permissions: 0.345 socket: 0.339 KVM: 0.247 PID: 0.228 boot: 0.220 files: 0.188 ARM: HCR.TSW traps are not implemented On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap data or unified cache maintenance instructions that operate by Set/Way." Quoting the ARM manual: If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped to EL2, reported using EC syndrome value 0x18. If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped to EL2, reported using EC syndrome value 0x03. However, QEMU does not trap those instructions/registers. This was tested on the branch master of the git repo. Patch posted: https://