other: 0.791 graphic: 0.693 semantic: 0.615 device: 0.515 PID: 0.442 performance: 0.412 debug: 0.360 socket: 0.349 boot: 0.321 vnc: 0.294 network: 0.261 permissions: 0.248 files: 0.128 KVM: 0.094 RISCV dynamic rounding mode is not behaving correctly Hello, I’ve gone through the RISC-V code in latest QEMU release (qemu-5.0.0-rc2) and when checking the Floating point encodings I found the rounding mode is only updated if the opcode field “rm” is changed “ctx->frm == rm”. But according to RISC-V Volume I: Unprivileged ISA, there’s a dynamic mode when rm=7 where the rounding mode is set with frm value. So for the same rm value (=7) and when changing frm value seeking different rounding modes, and according to the below code, the rounding mode won’t be updated. Please correct me if I got this implementation wrong. static void gen_set_rm(DisasContext *ctx, int rm) { TCGv_i32 t0; if (ctx->frm == rm) { return; } ctx->frm = rm; t0 = tcg_const_i32(rm); gen_helper_set_rounding_mode(cpu_env, t0); tcg_temp_free_i32(t0); } My testcase: I set statically the rm field in the instruction to 7 and before this execution I changed the value of frm field in fcsr register. For the 1st time it worked (according to the code above, the rm is updated so the round mode will also be updated). But when changing fcsr register an re-execute the instruction, there's no difference and the rounding mode is the same like the previous frm value. After checking RISCY RTL code, i found the implementation is straight forward as stated in specs as follows: if (FPU == 1) begin if (fp_rnd_mode == 3'b111) apu_flags = frm_i; else apu_flags = fp_rnd_mode; end else where fp_rnd_mode is the round mode field in the instruction opcode. This does look like incorrect behaviour. I have sent a patch to the mailing list. You can see the patch here: https://