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Tricore: wrong implementation of OPC1_16_SRO_LD_H in target/tricore/translate.c
Description of problem:
The translation of the 16bit opcode LD.HD[15], A[b], off4 (SRO) is not done properly.
Page 210 of
https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8
as 
D[15] = sign_ext(M(A[b] + zero_ext(2 * off4), half-word));
1) Implemented in target/tricore/translate.c as
    case OPC1_16_SRO_LD_H:
        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
        break;

2) Should be 
    case OPC1_16_SRO_LD_H:
        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
        break;

Detected: 
testsuite gcc9.1.0 delta analysis of Infineon Instruction Set Simulator vs. qemu-system-tricore
fix from 2) is successfull

Confidence Level for bugfix high.
Is according to spec. and in line with reference Instruction Set Simulator from Infineon.

Motivation
Reexecution of gcc/g++/libstdc++ testsuites with qemu

I honor the implementation work which was done by bkoppelmann, vo_lumit@gmx.de