semantic: 0.197
other: 0.162
graphic: 0.121
device: 0.081
debug: 0.065
PID: 0.054
vnc: 0.051
network: 0.048
boot: 0.044
performance: 0.042
socket: 0.041
files: 0.040
KVM: 0.029
permissions: 0.027
debug: 0.786
files: 0.050
other: 0.035
performance: 0.033
PID: 0.022
network: 0.014
device: 0.012
semantic: 0.011
boot: 0.010
graphic: 0.008
socket: 0.007
permissions: 0.005
vnc: 0.005
KVM: 0.004

[riscv/regression] Missing tlb flush introduced in refactoring

Hello,

In qemu-system-riscv64, following a QEMU update, I get all sort of weird and not easily reproducible crashes in my risc-v guest.

I have bissected this issue to commit c7b951718815694284501ed01fec7acb8654db7b.
Some TLB flushes were removed in the following places:
target/riscv/cpu_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice)
target/riscv/op_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice)

Adding TLB flushes in all 4 places fixes the issues for me.

Hello,

Thanks for reporting a bug.

Can you please include details to reproduce the problems that you are seeing? This includes images and command line arguments.

Do you also mind including the diff of what fixes the problem for you?

Alistair

It has been solved thanks to the mailing-list members.