other: 0.230 debug: 0.193 semantic: 0.158 device: 0.088 vnc: 0.053 performance: 0.053 graphic: 0.038 permissions: 0.035 network: 0.031 socket: 0.030 files: 0.026 PID: 0.025 KVM: 0.022 boot: 0.018 debug: 0.887 files: 0.019 other: 0.018 semantic: 0.011 performance: 0.011 network: 0.010 device: 0.009 KVM: 0.007 boot: 0.006 socket: 0.005 PID: 0.005 vnc: 0.005 graphic: 0.004 permissions: 0.004 ARM: HCR.TSW traps are not implemented On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap data or unified cache maintenance instructions that operate by Set/Way." Quoting the ARM manual: If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped to EL2, reported using EC syndrome value 0x18. If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped to EL2, reported using EC syndrome value 0x03. However, QEMU does not trap those instructions/registers. This was tested on the branch master of the git repo. Patch posted: https://