architecture: 0.969 arm: 0.935 kernel: 0.912 graphic: 0.903 device: 0.901 register: 0.853 semantic: 0.833 performance: 0.815 peripherals: 0.798 network: 0.755 permissions: 0.709 socket: 0.707 files: 0.660 vnc: 0.648 boot: 0.648 VMM: 0.642 mistranslation: 0.619 virtual: 0.612 ppc: 0.585 risc-v: 0.539 PID: 0.516 user-level: 0.494 debug: 0.485 x86: 0.432 hypervisor: 0.397 TCG: 0.397 i386: 0.302 assembly: 0.187 KVM: 0.100 -------------------- arm: 0.997 architecture: 0.868 kernel: 0.428 debug: 0.108 virtual: 0.067 TCG: 0.035 assembly: 0.032 VMM: 0.026 user-level: 0.022 register: 0.019 files: 0.016 network: 0.015 device: 0.009 semantic: 0.008 hypervisor: 0.008 PID: 0.008 socket: 0.006 risc-v: 0.005 peripherals: 0.003 vnc: 0.003 performance: 0.002 permissions: 0.001 boot: 0.001 graphic: 0.001 mistranslation: 0.000 KVM: 0.000 ppc: 0.000 i386: 0.000 x86: 0.000 ARM instruction "srs" wrong behaviour Quote from ARM Architecture Reference Manual ARMv7-A and ARMv7-R : "Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode" Problem: When executing this instruction, the register stored is CPSR instead of SPSR. Context: Using QEMU 1.2.0 to simulate a Zynq application (processor Cortex-a9 mpcore) with the following command line: qemu-system-arm -M xilinx-zynq-a9 -m 512 -serial null -serial mon:stdio -dtb /home/vcesson/workspace/xilinx_zynq.dtb -kernel install/tests/io/serial/current/tests/serial2 -S -s -nographic It looks like this is only a problem in Thumb mode; the equivalent bug in ARM mode was fixed in commit c67b6b71 back in 2009. Can you make the test case dtb and image available? That would help in testing... Thanks -- I've submitted a patch which fixes this: http://patchwork.ozlabs.org/patch/220748/ If you'd like to give me a name/email [format "Full Name