architecture: 0.909
arm: 0.897
register: 0.755
peripherals: 0.743
device: 0.723
mistranslation: 0.638
network: 0.572
socket: 0.561
ppc: 0.555
vnc: 0.554
permissions: 0.548
kernel: 0.528
risc-v: 0.524
files: 0.521
TCG: 0.515
graphic: 0.510
performance: 0.472
boot: 0.426
semantic: 0.425
PID: 0.419
hypervisor: 0.415
VMM: 0.403
KVM: 0.396
user-level: 0.389
virtual: 0.327
assembly: 0.323
debug: 0.305
i386: 0.274
x86: 0.173
--------------------
arm: 0.999
register: 0.395
architecture: 0.171
kernel: 0.082
TCG: 0.032
device: 0.029
assembly: 0.029
semantic: 0.028
virtual: 0.021
files: 0.021
debug: 0.018
PID: 0.015
VMM: 0.013
peripherals: 0.012
hypervisor: 0.006
vnc: 0.005
performance: 0.005
socket: 0.003
user-level: 0.003
KVM: 0.002
network: 0.002
boot: 0.001
permissions: 0.001
graphic: 0.001
mistranslation: 0.001
risc-v: 0.000
i386: 0.000
x86: 0.000
ppc: 0.000

arm emulation of HCR.TID3 traps are not implemented

On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3, which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers. However, setting that HCR bit has no effect and accesses to those ID registers are not trapped to EL2 with an EC syndrome value of 0x18.

Yes, we don't currently implement most of the 'trap system register access' bits in HCR_EL2. Last time I checked we were missing TID0 TID1 TID2 TID3 TIDCP TAC TSW TPC TPU TTLB TVM TRVM TDZ, but it's possible we've implemented one or two of those since then.


TID3 trapping should be mostly fixed for 4.2 -- we will trap accesses to all the coprocessor/sysreg ID registers that TID3 covers. Trapping of aarch32 MVFR* (which are accessed via vmrs) will not make it into this release, but should be in 5.0.


The last bit of TID3 trapping is now in QEMU git master and will be in 5.0.