device: 0.832 register: 0.732 graphic: 0.731 mistranslation: 0.661 architecture: 0.568 performance: 0.485 semantic: 0.482 risc-v: 0.454 kernel: 0.412 ppc: 0.408 vnc: 0.357 arm: 0.312 PID: 0.285 permissions: 0.282 debug: 0.269 TCG: 0.258 socket: 0.257 boot: 0.242 VMM: 0.204 user-level: 0.190 files: 0.183 network: 0.145 peripherals: 0.145 i386: 0.123 x86: 0.067 KVM: 0.013 assembly: 0.012 hypervisor: 0.006 virtual: 0.006 Opentitan Timer ignores COMPARE_UPPER0/COMPARE_LOWER0 Description of problem: In a bare metal application, running on an emulated Opentitan board, if you set a timer interrupt threshold by writing to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before writing to `rv_timer.CTRL` to start the timer, then the interrupt does not fire. If you write to the `COMPARE_*` registers *after* starting the timer by writing to `CTRL`, then the interrupt fires correctly. I think the explanation is that [ibex_timer_update_irqs](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L61) has an early return if `rv_timer.CTRL` is not set. As a result, although writes to `COMPARE_*` always call `ibex_timer_update_irqs`, they don't have their intended side-effects before `CTRL` is unset. Steps to reproduce: Write to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before you have set `rv_timer.CTRL`. Observe that no timer interrupt occurs.