graphic: 0.829
register: 0.784
mistranslation: 0.779
files: 0.757
device: 0.742
semantic: 0.708
architecture: 0.702
ppc: 0.622
network: 0.604
vnc: 0.535
i386: 0.387
TCG: 0.369
kernel: 0.341
virtual: 0.327
performance: 0.314
PID: 0.305
arm: 0.305
boot: 0.303
VMM: 0.292
user-level: 0.275
debug: 0.273
permissions: 0.270
risc-v: 0.216
peripherals: 0.216
socket: 0.199
x86: 0.163
hypervisor: 0.066
KVM: 0.037
assembly: 0.003

Opentitan timer layout incorrect
Description of problem:
It looks as if some of the timer register offsets here are incorrect:

https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L37

Compare with:

https://opentitan.org/book/hw/ip/rv_timer/doc/registers.html

I suspect they're out of date. The documentation link on line 7 is not working anymore - the current documentation URL for Opentitan is the one just given.

It might also make sense to rename this file `opentitan_timer.c`, instead of  `ibex_timer.c`. The timer is an Opentitan hardware IP block, rather than a feature of the Ibex CPU.