register: 0.913
device: 0.872
graphic: 0.721
vnc: 0.666
mistranslation: 0.649
kernel: 0.641
architecture: 0.617
network: 0.614
ppc: 0.604
hypervisor: 0.518
performance: 0.513
risc-v: 0.480
socket: 0.464
peripherals: 0.443
files: 0.427
semantic: 0.354
x86: 0.279
permissions: 0.279
debug: 0.270
i386: 0.252
PID: 0.237
arm: 0.220
TCG: 0.205
boot: 0.187
VMM: 0.181
assembly: 0.165
user-level: 0.152
KVM: 0.115
virtual: 0.088
--------------------
register: 0.901
arm: 0.594
debug: 0.550
x86: 0.238
device: 0.215
kernel: 0.146
TCG: 0.134
hypervisor: 0.111
VMM: 0.091
i386: 0.087
peripherals: 0.070
files: 0.069
PID: 0.024
architecture: 0.023
virtual: 0.021
assembly: 0.016
user-level: 0.015
KVM: 0.010
semantic: 0.008
performance: 0.007
ppc: 0.005
socket: 0.005
risc-v: 0.004
network: 0.004
boot: 0.003
vnc: 0.003
permissions: 0.002
graphic: 0.001
mistranslation: 0.001

Incorrect RNG_CTRL and RNG_DATA_OUTPUT register offets for Aspeed AST2600 A3
Description of problem:
hw/misc/aspeed_scu.c has the following lines:

#define AST2600_RNG_CTRL          TO_REG(0x524)
#define AST2600_RNG_DATA          TO_REG(0x540)

The Datasheet for the AST2600 A3 lists the offsets as 0x520 for RNG_CTRL and 0x524 for RNG_DATA.  I can confirm that these addresses are correct on the hardware.  I don't know if the offsets changed from a previous revision, but since qemu fills the SILICON_REV register with the AST2600_A3_SILICON_REV value for the AST2600, it makes sense to me that it would use the A3 register offsets.
Steps to reproduce:
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Additional information: