[RV64] JIT of vector instructions
RISC-V is still a young architecture that has more extensions to be added. Currently, the “V” vector extension is in a [frozen state](https://github.com/riscv/riscv-v-spec/tree/57998875a3aebfe53407e82f1ec9fda0fef746c7) and is expected to be ratified in the near future. T-Head has implemented a draft version (namely 0.7.1) of the V extension in their cores before, but apparently this is not widely adopted by most distros.

As a result, we still lack real-world support for the (stable) vector extension as of now. This poses a challenge if we want to directly translate ARM neon instructions to their RISC-V V counterparts. Should we leave these instructions to the emulation interpreter or use scalar instructions as a workaround?