SRA inserts arbitrary move for some reason?
Simple unit test to see the issue.
```asm
%ifdef CONFIG
{
  "RegData": {
    "RAX": "0x4"
  }
}
%endif

mov rax, 1
mov rbx, 1
shld rax, rbx, 2

hlt
```

Resulting IR for the shld instruction.
```
                (%3 i0) BeginBlock %2(Invalid)
                %4(GPRFixed3) i64 = LoadRegister #0x0, #0x20, GPR, GPRFixed, u8:Tmp:Size
                %5(GPR0) i64 = LoadRegister #0x0, #0x8, GPR, GPRFixed, u8:Tmp:Size
                %6(GPRFixed0) i64 = Extr %5(GPR0) i64, %4(GPRFixed3) i64, #0x3e
                ...
```

As seen, the first source to the `Extr` IR op doesn't get assigned to static register allocation for some reason.
This results in a redundant move when the Arm64 JIT emits code.
```asm
0x0000ffff840800a4  aa0403f4            mov x20, x4
0x0000ffff840800a8  93c7fa84            extr x4, x20, x7, #62
```

Unknown how many places in the JIT this causes arbitrary moves. Noticed while writing #2779