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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2017-02-12 18:51:29 +0100
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2017-02-12 18:51:29 +0100
commit4cadfcf63e4e74918f022d24c5efa56aafbaff12 (patch)
tree248eef50d915fc3eb8fec634318f6492af6d0f27
parentbf4eeb159e07333b90d81ca1ff26591ad9f81fc2 (diff)
downloadfocaccia-miasm-4cadfcf63e4e74918f022d24c5efa56aafbaff12.tar.gz
focaccia-miasm-4cadfcf63e4e74918f022d24c5efa56aafbaff12.zip
Jitter: remove useless segm trunc
-rw-r--r--miasm2/jitter/emulatedsymbexec.py6
-rw-r--r--miasm2/jitter/llvmconvert.py7
2 files changed, 4 insertions, 9 deletions
diff --git a/miasm2/jitter/emulatedsymbexec.py b/miasm2/jitter/emulatedsymbexec.py
index ff9e5eaa..9ece5ff5 100644
--- a/miasm2/jitter/emulatedsymbexec.py
+++ b/miasm2/jitter/emulatedsymbexec.py
@@ -103,13 +103,11 @@ class EmulatedSymbExec(symbexec):
     # CPU specific simplifications
     def _simp_handle_segm(self, e_s, expr):
         """Handle 'segm' operation"""
-        if expr.op != "segm":
+        if not expr.is_op_segm():
             return expr
         segm_nb = int(expr.args[0])
         segmaddr = self.cpu.get_segm_base(segm_nb)
-        return e_s(m2_expr.ExprOp("+",
-                                  m2_expr.ExprInt(segmaddr, expr.size),
-                                  expr.args[1]))
+        return e_s(m2_expr.ExprInt(segmaddr, expr.size) + expr.args[1])
 
     def _simp_handle_cpuid(self, e_s, expr):
         """From miasm2/jitter/vm_mngr.h: cpuid"""
diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py
index bc04689c..527dc733 100644
--- a/miasm2/jitter/llvmconvert.py
+++ b/miasm2/jitter/llvmconvert.py
@@ -735,11 +735,8 @@ class LLVMFunction():
 
                 ret = builder.call(fc_ptr,
                                    [self.local_vars["jitcpu"]] + casted_args)
-                # Ret size is not expr.size on segm2addr (which is the size of
-                # the segment, for instance 16 bits), but the size of an addr
-                ret_size = self.llvm_context.PC.size
-                if ret.type.width > ret_size:
-                    ret = builder.trunc(ret, LLVMType.IntType(ret_size))
+                if ret.type.width > expr.size:
+                    ret = builder.trunc(ret, LLVMType.IntType(expr.size))
                 self.update_cache(expr, ret)
                 return ret