diff options
| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2021-01-09 18:03:12 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2021-01-09 18:03:12 +0100 |
| commit | 8f09c52c0f2fb5357f7ca2b0a4d067b54a9de00c (patch) | |
| tree | d94672d5a04d8b0bf266aba626dd2efd55daef92 | |
| parent | f81cc38070485c59e3730c4f941b13232039db94 (diff) | |
| download | focaccia-miasm-8f09c52c0f2fb5357f7ca2b0a4d067b54a9de00c.tar.gz focaccia-miasm-8f09c52c0f2fb5357f7ca2b0a4d067b54a9de00c.zip | |
Aarch64: add ldar/stlr
| -rw-r--r-- | miasm/arch/aarch64/sem.py | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/miasm/arch/aarch64/sem.py b/miasm/arch/aarch64/sem.py index 8a084ea7..8cbab90b 100644 --- a/miasm/arch/aarch64/sem.py +++ b/miasm/arch/aarch64/sem.py @@ -1270,7 +1270,10 @@ def get_mem_access(mem): updt = None if isinstance(mem, ExprOp): if mem.op == 'preinc': - addr = mem.args[0] + mem.args[1] + if len(mem.args) == 1: + addr = mem.args[0] + else: + addr = mem.args[0] + mem.args[1] elif mem.op == 'segm': base = mem.args[0] op, (reg, shift) = mem.args[1].op, mem.args[1].args @@ -2206,11 +2209,13 @@ mnemo_func.update({ 'ldrsh': ldrsh, 'ldrsw': ldrsw, + 'ldar': ldr, # TODO memory barrier 'ldarb': ldrb, 'ldaxrb': ldaxrb, 'stlxrb': stlxrb, + 'stlr': l_str, # TODO memory barrier 'stlrb': stlrb, 'stlxr': stlxr, |